mul_booth.v

基于BOOTH的32位快速乘法器的设计源码

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:06:05 08/15/2007 
// Design Name: 
// Module Name:    mul_booth 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mul_booth(a, b, m);
    input [31:0] a;
    input [31:0] b;
    output [63:0] m;


wire [63:0] tar;
wire [69:0] tes;
wire [70:0] tec;

assign m=tar;

wire  [70:0] tag,tap;
wire  [70:1] tac;
wire  [17:0] tag_S0,tap_S0;
wire  [ 4:0] tag_S1,tap_S1;
wire  [17:1] tac_S1;
wire  [ 4:1] tac_S2;
assign tar=tap^{tac,1'b0};
assign tag=tes&tec;
assign tap=tes^tec;
carry_leading_4 cl_s0_p0(tag[ 3: 0],tap[ 3: 0],1'b0,tac[ 4: 1],tag_S0[0],tap_S0[0]),
                cl_s0_p1(tag[ 7: 4],tap[ 7: 4],tac_S1[1],tac[ 8: 5],tag_S0[1],tap_S0[1]),
                cl_s0_p2(tag[11: 8],tap[11: 8],tac_S1[2],tac[12: 9],tag_S0[2],tap_S0[2]),
                cl_s0_p3(tag[15:12],tap[15:12],tac_S1[3],tac[16:13],tag_S0[3],tap_S0[3]),
                cl_s0_p4(tag[19:16],tap[19:16],tac_S1[4],tac[20:17],tag_S0[4],tap_S0[4]),
                cl_s0_p5(tag[23:20],tap[23:20],tac_S1[5],tac[24:21],tag_S0[5],tap_S0[5]),
                cl_s0_p6(tag[27:24],tap[27:24],tac_S1[6],tac[28:25],tag_S0[6],tap_S0[6]),
                cl_s0_p7(tag[31:28],tap[31:28],tac_S1[7],tac[32:29],tag_S0[7],tap_S0[7]),
                cl_s0_p8(tag[35:32],tap[35:32],tac_S1[8],tac[36:33],tag_S0[8],tap_S0[8]),
                cl_s0_p9(tag[39:36],tap[39:36],tac_S1[9],tac[40:37],tag_S0[9],tap_S0[9]),
                cl_s0_p10(tag[43:40],tap[43:40],tac_S1[10],tac[44:41],tag_S0[10],tap_S0[10]),
                cl_s0_p11(tag[47:44],tap[47:44],tac_S1[11],tac[48:45],tag_S0[11],tap_S0[11]),
                cl_s0_p12(tag[51:48],tap[51:48],tac_S1[12],tac[52:49],tag_S0[12],tap_S0[12]),
                cl_s0_p13(tag[55:52],tap[55:52],tac_S1[13],tac[56:53],tag_S0[13],tap_S0[13]),
                cl_s0_p14(tag[59:56],tap[59:56],tac_S1[14],tac[60:57],tag_S0[14],tap_S0[14]),
                cl_s0_p15(tag[63:60],tap[63:60],tac_S1[15],tac[64:61],tag_S0[15],tap_S0[15]),
                cl_s0_p16(tag[67:64],tap[67:64],tac_S1[16],tac[68:65],tag_S0[16],tap_S0[16]),
                cl_s0_p17(tag[70:68],tap[70:68],tac_S1[17],tac[70:69],tag_S0[17],tap_S0[17]);
               
carry_leading_4 cl_s1_p0(tag_S0[3:0], tap_S0[3:0], 1'b0,tac_S1[4:1], tag_S1[0],tap_S1[0]),
                cl_s1_p1(tag_S0[7:4], tap_S0[7:4], tac_S2[1],tac_S1[8:5], tag_S1[1],tap_S1[1]),
                cl_s1_p2(tag_S0[11:8],tap_S0[11:8],tac_S2[2],tac_S1[12:9],tag_S1[2],tap_S1[2]),
                cl_s1_p3(tag_S0[15:12],tap_S0[15:12],tac_S2[3],tac_S1[16:13], tag_S1[3],tap_S1[3]),
                cl_s1_p4(tag_S0[17:16],tap_S0[17:16],tac_S2[4],tac_S1[17],tag_S1[4],tap_S1[4]);

carry_leading_4 cl_s2_p0(tag_S1,tap_S1,1'b0,tac_S2,,);

wire [32:0] s0;
wire [34:2] s1;
wire [36:4] s2;
wire [38:6] s3;
wire [40:8] s4;
wire [42:10] s5;
wire [44:12] s6;
wire [46:14] s7;
wire [48:16] s8;
wire [50:18] s9;
wire [52:20] s10;
wire [54:22] s11;
wire [56:24] s12;
wire [58:26] s13;
wire [60:28] s14;
wire [62:30] s15;
wire [64:32] s16;
wire [33:0] c;


booth_encode booth_i0({b[1:0],1'b0},a,s0,c[0]),
             booth_i1(b[3:1],a,s1,c[2]),
             booth_i2(b[5:3],a,s2,c[4]),
             booth_i3(b[7:5],a,s3,c[6]),
             booth_i4(b[9:7],a,s4,c[8]),
             booth_i5(b[11:9],a,s5,c[10]),
             booth_i6(b[13:11],a,s6,c[12]),
             booth_i7(b[15:13],a,s7,c[14]),
             booth_i8(b[17:15],a,s8,c[16]),
             booth_i9(b[19:17],a,s9,c[18]),
             booth_i10(b[21:19],a,s10,c[20]),
             booth_i11(b[23:21],a,s11,c[22]),
             booth_i12(b[25:23],a,s12,c[24]),
             booth_i13(b[27:25],a,s13,c[26]),
             booth_i14(b[29:27],a,s14,c[28]),
             booth_i15(b[31:29],a,s15,c[30]),
             booth_i16({1'b0,1'b0,b[31]},a,s16,c[32]);

wire [41:0] result_1_1;
wire [42:0] carry_1_1;
compress4_2  compress4_2_i0_1( {~c[0],c[0],c[0],s0[32:0]},
                               {1'b1,~c[2],s1[34:2],2'b00},
                               {1'b1,~c[4],s2[36:4],4'b0000},
                               {1'b1,~c[6],s3[38:6],6'b0000_00},
                               result_1_1,
                               carry_1_1);
defparam compress4_2_i0_1.dw=40;

wire [49:0] result_1_2;
wire [50:0] carry_1_2;
compress4_2  compress4_2_i0_2( {1'b1,~c[8],s4[40:8],8'b0000_0000},
                               {1'b1,~c[10],s5[42:10],10'b0000_0000_00},
                               {1'b1,~c[12],s6[44:12],12'b0000_0000_0000},
                               {1'b1,~c[14],s7[46:14],14'b0000_0000_0000_00},
                               result_1_2,
                               carry_1_2);
defparam compress4_2_i0_2.dw=48;

wire [53:0] result_2_1;
wire [54:0] carry_2_1;
compress4_2  compress4_2_i1_1( result_1_1,
                               {carry_1_1,1'b0},
                               {1'b1,~c[16],s8[48:16],16'b0000_0000_0000_0000},
                               {1'b1,~c[18],s9[50:18],18'b0000_0000_0000_0000_00},
                               result_2_1,
                               carry_2_1);
defparam compress4_2_i1_1.dw=52;

wire [57:0] result_2_2;
wire [58:0] carry_2_2;
compress4_2  compress4_2_i1_2( result_1_2,
                               {carry_1_2,1'b0},
                               {1'b1,~c[20],s10[52:20],20'b0000_0000_0000_0000_0000},
                              {1'b1,~c[22],s11[54:22],22'b0000_0000_0000_0000_0000_00},
                              result_2_2,
                              carry_2_2);
defparam compress4_2_i1_2.dw=56;

wire [61:0] result_3_1;
wire [62:0] carry_3_1;
compress4_2  compress4_2_i2_1( result_2_1,
                               {carry_2_1,1'b0},
                               {1'b1,~c[24],s12[56:24],24'b0000_0000_0000_0000_0000_0000},
                               {1'b1,~c[26],s13[58:26],26'b0000_0000_0000_0000_0000_0000_00},
                               result_3_1,
                               carry_3_1);
defparam compress4_2_i2_1.dw=60;

wire [64:0] result_3_2;
wire [65:0] carry_3_2;
compress4_2  compress4_2_i2_2( result_2_2,
                               {carry_2_2,1'b0},
                               {1'b1,~c[28],s14[60:28],28'b0000_0000_0000_0000_0000_0000_0000},
                               {~c[30],s15[62:30],30'b0000_0000_0000_0000_0000_0000_0000_00},
                               result_3_2,
                               carry_3_2);
defparam compress4_2_i2_2.dw=63;

wire [67:0] result_4_1;
wire [67:0] carry_4_1;
compress4_2  compress4_2_i3_1( result_3_1,
                               {carry_3_1,1'b0},result_3_2,{carry_3_2,1'b0},
                               result_4_1,
                               carry_4_1);
defparam compress4_2_i3_1.dw=66;

wire [69:0] result_4_2;
wire [70:0] carry_4_2;
compress4_2  compress4_2_i3_2( c,result_4_1,
                               {carry_4_1,1'b0},
                               {s16[64:32],32'b0000_0000_0000_0000_0000_0000_0000_0000},
                               result_4_2,carry_4_2);
defparam compress4_2_i3_2.dw=68;
assign tes=result_4_2;
assign tec={carry_4_2,1'b0};
endmodule

module booth_encode(encode,source,result,carry);
input [2:0] encode;
input [31:0] source;
output [32:0] result;
output carry;
wire add_sub,once_valid,twice_enable,zero_enable;
wire [32:0] result;
wire carry;
assign add_sub = encode[2] ^ 1'b0;
assign once_valid = encode[1] ^ encode[0];
assign twice_enable = ((encode == 3'b011) | (encode == 3'b100));
assign zero_enable=((encode == 3'b000) | (encode == 3'b111));
assign result = ( ( {encode[2],{{source} ^ {32{add_sub}}}} ) & {33{once_valid}} ) |
               (( { {{source[31:0]} ^ {32{add_sub}}},encode[2]} ) & {33{twice_enable}}) | 
               ( ( {encode[2],{ {32{1'b0}}^ {32{add_sub}} } } )& {33{zero_enable}} );
assign carry =encode[2] ^ 1'b0;
endmodule

module compress4_2(i1,i2,i3,i4,result,carry);
parameter dw=6;
input [dw:0] i1,i2,i3,i4;
output [(dw+1):0] result;
output [(dw+2):1] carry;
wire [(dw+1):0] result;
wire [(dw+2):1] carry;
wire [dw:0] m1;
wire [(dw+1):1] m2;
assign m1=i1^i2^i3;
assign m2=i1&i2|i1&i3|i2&i3;
assign result=m1^{m2,1'b0}^i4;
assign carry=m1&i4|m1&({m2,1'b0})|({m2,1'b0})&i4;
endmodule

module carry_leading_4(g,p,ci,c,gx,px);
input [3:0] g,p;
input ci;
output[4:1] c;
output gx,px;
assign c[1]=g[0]|p[0]&ci;
assign c[2]=g[1]|p[1]&g[0]|p[1]&p[0]&ci;
assign c[3]=g[2]|p[2]&g[1]|p[2]&p[1]&g[0]|p[2]&p[1]&p[0]&ci;
assign c[4]=gx|px&ci;
assign gx=g[3]|p[3]&g[2]|p[3]&p[2]&g[1]|p[3]&p[2]&p[1]&g[0];
assign px=p[3]&p[2]&p[1]&p[0];
endmodule