vhdl_jishuqi.txt

一路24位计数器,cpu可直接读写计数器的计数值.

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xiaoxiaocui is
    Port ( D : inout  STD_LOGIC_VECTOR (7 downto 0);
           wr : in  STD_LOGIC;
           rd : in  STD_LOGIC;
           cs : in  STD_LOGIC;
           a0 : in  STD_LOGIC;
           a1 : in  STD_LOGIC;
           maichong_in : in  STD_LOGIC);
end xiaoxiaocui;

architecture Behavioral of xiaoxiaocui is
signal internal_bus_in : std_logic_vector(7 downto 0);
signal internal_bus_out: std_logic_vector(7 downto 0);
signal crreg           : std_logic_vector(23 downto 0);--chushizhi
signal olreg           : std_logic_vector(23 downto 0);--suocun
signal cereg           : std_logic_vector(23 downto 0);--dangqianzhi
signal conter_en       : std_logic;--shineng
signal con             : std_logic_vector(7 downto 0);--kongzhizi
signal ref             : std_logic;--zhaungzai
begin
--*****************************************************************************************
 DATE_CATHE:PROCESS(wr,rd,cs)
        BEGIN
       IF(wr='0' AND cs='0' )THEN
         internal_bus_out<=D;
		  ELSIF(rd='0' AND  cs='0')THEN
		    D<=internal_bus_in;
		 ELSE
		    D<="ZZZZZZZZ";
		 END IF;
    END PROCESS DATE_CATHE;
--*****************************************************************************************
READE_DATE: PROCESS(a0,a1)
   VARIABLE   ad : std_logic_vector(1 downto 0);
     BEGIN
	    IF (cs='0' AND rd='0')THEN
               ad:=a1&a0;
		    IF ad ="00" THEN
		      internal_bus_in <=olreg(7 downto 0);
		    ELSIF ad ="01" THEN
			   internal_bus_in <=olreg(15 downto 8);
		    ELSIF ad ="10" THEN
            internal_bus_in <=olreg(23 downto 16);             
		    END IF;
		 END IF;
	END PROCESS READE_DATE;
--*****************************************************************************************
 COUNTER: PROCESS(conter_en,maichong_in)
     BEGIN
	   
		IF conter_en='0' THEN
		  cereg<="111111111111111111111111";    
		ELSIF(maichong_in'EVENT AND maichong_in='0')THEN
		     if ref='1' then
              cereg<=crreg; 
           end if;    
              IF cereg<"111111111111111111111111" THEN 
			               cereg<=cereg+1; 
		        ELSE 
			         cereg<="111111111111111111111111";
		        END IF;         
         
		END IF ;	
END PROCESS COUNTER;
--*****************************************************************************************
 CTR_REG: PROCESS(wr,cs)
   VARIABLE   wr_flag : std_logic_vector(7 downto 0);
	VARIABLE   ad : std_logic_vector(1 downto 0);
   BEGIN
     
		IF(wr='0' and cs='0')THEN
        wr_flag:=D(7 downto 0);  ad:=a1&a0;
	   END IF; 
      IF(wr'event and wr='1')THEN 
		  IF(ad="11"and cs='0')THEN
		     IF(wr_flag/="00000000")THEN
               con<=internal_bus_out;
               conter_en<='0';
		         else 
				   olreg<=cereg;
            end if;
   	  elsif(ad="00" and cs='0')then
              crreg(7 downto 0)<=internal_bus_out;                 
		  elsif(ad="01" and cs='0')then
              crreg(15 downto 8)<=internal_bus_out;
        elsif(ad="10"and cs='0')then
              crreg(23 downto 16)<=internal_bus_out; 
			     conter_en<='1'; 
               
        END IF;
		  
     END IF;
     
   END PROCESS CTR_REG; 
--*****************************************************************************************
REF0:PROCESS(maichong_in)
        BEGIN
        IF( conter_en='1')THEN
         ref<='1';
		  ELSIF(maichong_in'EVENT AND maichong_in='0')THEN
		     if ref<='1' then
			    ref<='0';
			  end if;
		 END IF;
    END PROCESS REF0;
--*****************************************************************************************
end Behavioral;