ping.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 594 行 · 第 1/2 页

----------------------------------------------------------------------------
--
--  File:   ping.vhd
--  Rev:    3.0.0
--
--  This is an example user application for use with the Xilinx PCI
--  initiator.  The design has been tested with the Synopsys design
--  flow.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity ping64 is
  port (-- Interface to PCI Logicore.
        FRAMEQ_N        : in    std_logic;
        REQ64Q_N        : in    std_logic;
        TRDYQ_N         : in    std_logic;
        IRDYQ_N         : in    std_logic;
        STOPQ_N         : in    std_logic;
        DEVSELQ_N       : in    std_logic;
        ACK64Q_N        : in    std_logic;

        ADDR            : in    std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);

        CFG_VLD         : in    std_logic;
        CFG_HIT         : in    std_logic;
        C_TERM          : out   std_logic;
        C_READY         : out   std_logic;

        ADDR_VLD        : in    std_logic;
        BASE_HIT        : in    std_logic_vector(  7 downto 0);

        S_CYCLE64       : in    std_logic;
        S_TERM          : out   std_logic;
        S_READY         : out   std_logic;
        S_ABORT         : out   std_logic;
        S_WRDN          : in    std_logic;
        S_SRC_EN        : in    std_logic;
        S_DATA_VLD      : in    std_logic;
        S_CBE           : in    std_logic_vector(  7 downto 0);
        PCI_CMD         : in    std_logic_vector( 15 downto 0);

        REQUEST         : out   std_logic;
        REQUEST64       : out   std_logic;
        REQUESTHOLD     : out   std_logic;
        COMPLETE        : out   std_logic;

        M_WRDN          : out   std_logic;
        M_READY         : out   std_logic;
        M_SRC_EN        : in    std_logic;
        M_DATA_VLD      : in    std_logic;
        M_CBE           : out   std_logic_vector(  7 downto 0);

        TIME_OUT        : in    std_logic;
        M_FAIL64        : in    std_logic;
        CFG_SELF        : out   std_logic;

        M_DATA          : in    std_logic;
        DR_BUS          : in    std_logic;
        I_IDLE          : in    std_logic;
        M_ADDR_N        : in    std_logic;
        IDLE            : in    std_logic;
        B_BUSY          : in    std_logic;
        S_DATA          : in    std_logic;
        BACKOFF         : in    std_logic;

        SLOT64          : out   std_logic;
        INTR_N          : out   std_logic;
        PERRQ_N         : in    std_logic;
        SERRQ_N         : in    std_logic;
        KEEPOUT         : out   std_logic;

        CSR             : in    std_logic_vector( 39 downto 0);
        SUB_DATA        : out   std_logic_vector( 31 downto 0);
        CFG             : in    std_logic_vector(255 downto 0);

        RST             : in    std_logic;
        CLK             : in    std_logic;

        -- Add user I/O ports here

        PING_DONE       : out   std_logic;
        PING_REQUEST32  : in    std_logic;
        PING_REQUEST64  : in    std_logic
  );
end ping64;


architecture rtl of ping64 is

  attribute syn_edif_bit_format : string;
  attribute syn_edif_scalar_format : string;
  attribute syn_noclockbuf : boolean;
  attribute syn_hier : string;
  attribute syn_edif_bit_format of rtl : architecture is "%u<%i>";
  attribute syn_edif_scalar_format of rtl : architecture is "%u";
  attribute syn_noclockbuf of rtl : architecture is true;
  attribute syn_hier of rtl : architecture is "hard";

  type   fsm_states is  (IDLE_S, WRITE32_S, READ32_S, WRITE64_S, READ64_S);
  signal ping_state     : fsm_states;
  signal nxt_ping_state : fsm_states;

  signal cfg_rd         : std_logic;
  signal bar0_rd        : std_logic;
  signal bar1_rd        : std_logic;
  signal bar2_rd        : std_logic;

  signal cfg_wr         : std_logic;
  signal bar0_wr        : std_logic;
  signal bar1_wr        : std_logic;
  signal bar2_wr        : std_logic;

  signal cfg_rd_cs      : std_logic;
  signal bar0_rd_cs     : std_logic;
  signal bar1_rd_cs     : std_logic;
  signal bar2_rd_cs     : std_logic;

  signal cfg_wr_cs      : std_logic;
  signal bar0_wr_cs     : std_logic;
  signal bar1_wr_cs     : std_logic;
  signal bar2_wr_cs     : std_logic;

  signal my_cfg_reg     : std_logic_vector(31 downto 0);
  signal oe_cfg_reg     : std_logic;
  signal en_cfg_reg     : std_logic;

  signal my_io_reg      : std_logic_vector(31 downto 0);
  signal oe_io_reg      : std_logic;

  signal my_mem_reg     : std_logic_vector(31 downto 0);
  signal oe_mem_reg     : std_logic;

  signal my_wide_reg    : std_logic_vector(63 downto 0);
  signal oe_wide_reg    : std_logic;

  signal xfer_len       : std_logic_vector( 3 downto 0);
  signal xfer_load_delay: std_logic;
  signal mdata_delay    : std_logic;
  signal feedback       : std_logic;
  signal pre_done       : std_logic;
  signal reg_preq32     : std_logic;
  signal reg_preq64     : std_logic;
  signal ns_done        : std_logic;
  signal mdata_fell     : std_logic;
  signal xfer_load      : std_logic;
  signal start32        : std_logic;
  signal start64        : std_logic;
  signal dir            : std_logic;
  signal cnt3           : std_logic;
  signal cnt2           : std_logic;
  signal cnt1           : std_logic;
  signal fin3           : std_logic;
  signal fin2           : std_logic;
  signal fin1           : std_logic;
  signal assert_complete: std_logic;
  signal hold_complete  : std_logic;

  signal my_init_reg    : std_logic_vector(63 downto 0);
  signal oe_init_reg    : std_logic;
  signal xlr, xlw, xhr  : std_logic;

  signal s_term_reg     : std_logic;
  signal s_ready_reg    : std_logic;
  signal m_ready_reg    : std_logic;
  signal intr_n_reg     : std_logic;

begin

  -----------------------------------------------------------------------
  -- This section contains the PCI interface decode.
  -----------------------------------------------------------------------

  IDENTIFY:
  process(RST, CLK)
  begin
    if RST = '1' then
      cfg_rd <= '0';
      cfg_wr <= '0';
      bar0_rd <= '0';
      bar0_wr <= '0';
      bar1_rd <= '0';
      bar1_wr <= '0';
      bar2_rd <= '0';
      bar2_wr <= '0';
    elsif (CLK'event and CLK = '1') then
      if CFG_HIT = '1' then
        cfg_rd <= not S_WRDN;
        cfg_wr <= S_WRDN;
      elsif S_DATA = '0' then
        cfg_rd <= '0';
        cfg_wr <= '0';
      end if;
      if BASE_HIT(0) = '1' then
        bar0_rd <= not S_WRDN;
        bar0_wr <= S_WRDN;
      elsif S_DATA = '0' then
        bar0_rd <= '0';
        bar0_wr <= '0';
      end if;
      if BASE_HIT(1) = '1' then
        bar1_rd <= not S_WRDN;
        bar1_wr <= S_WRDN;
      elsif S_DATA = '0' then
        bar1_rd <= '0';
        bar1_wr <= '0';
      end if;
      if BASE_HIT(2) = '1' then
        bar2_rd <= not S_WRDN;
        bar2_wr <= S_WRDN;
      elsif S_DATA = '0' then
        bar2_rd <= '0';
        bar2_wr <= '0';
      end if;
    end if;
  end process;
 
  cfg_rd_cs  <= cfg_rd;
  cfg_wr_cs  <= cfg_wr;
  bar0_rd_cs <= bar0_rd;
  bar0_wr_cs <= bar0_wr;
  bar1_rd_cs <= bar1_rd;
  bar1_wr_cs <= bar1_wr;
  bar2_rd_cs <= bar2_rd;
  bar2_wr_cs <= bar2_wr;


  -----------------------------------------------------------------------
  -- This section contains the CFG32 implementation.
  -----------------------------------------------------------------------

  WRITE_MY_CFG_REG:
  process(RST, CLK)
  begin
    if RST = '1' then my_cfg_reg <= "00000000000000000000000000000000";
    elsif (CLK'event and CLK = '1') then
      if S_DATA_VLD = '1' and cfg_wr_cs = '1' and en_cfg_reg = '1' then

        if S_CBE(0) = '0' then my_cfg_reg( 7 downto  0) <= ADIO( 7 downto  0);
        end if;
        if S_CBE(1) = '0' then my_cfg_reg(15 downto  8) <= ADIO(15 downto  8);
        end if;
        if S_CBE(2) = '0' then my_cfg_reg(23 downto 16) <= ADIO(23 downto 16);
        end if;
        if S_CBE(3) = '0' then my_cfg_reg(31 downto 24) <= ADIO(31 downto 24);
        end if;

      end if;
    end if;
  end process;

  en_cfg_reg <= ADDR(7) or ADDR(6);
  oe_cfg_reg <= en_cfg_reg and cfg_rd_cs and S_DATA and CFG(118);
  ADIO(31 downto 0) <= my_cfg_reg when (oe_cfg_reg = '1') else (others=>'Z');


  -----------------------------------------------------------------------
  -- This section contains the IO32 implementation.
  -----------------------------------------------------------------------
 
  WRITE_MY_IO_REG:
  process(RST, CLK)
  begin
    if RST = '1' then my_io_reg <= "00010000000100000001000000010000";
    elsif (CLK'event and CLK = '1') then
      if S_DATA_VLD = '1' and bar0_wr_cs = '1' then
 
        if S_CBE(0) = '0' then my_io_reg( 7 downto  0) <= ADIO( 7 downto  0);
        end if;
        if S_CBE(1) = '0' then my_io_reg(15 downto  8) <= ADIO(15 downto  8);
        end if;
        if S_CBE(2) = '0' then my_io_reg(23 downto 16) <= ADIO(23 downto 16);
        end if;
        if S_CBE(3) = '0' then my_io_reg(31 downto 24) <= ADIO(31 downto 24);
        end if;
 
      end if;
    end if;
  end process;
 
  oe_io_reg <= bar0_rd_cs and S_DATA;
  ADIO(31 downto 0) <= my_io_reg when (oe_io_reg = '1') else (others=>'Z');


  -----------------------------------------------------------------------
  -- This section contains the MEM32 implementation.  
  -----------------------------------------------------------------------