busrecord.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 98 行

------------------------------------------------------------------------
-- 
--  File:   busrecord.vhd
--  Rev:    3.0.0
--
--  This module saves the state of the PCI bus signals into a file at
--  every positive edge of the clock.  After simulation, the output
--  file can be compared to a known good file to verify the sameness
--  of two designs.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use STD.TEXTIO.ALL;


entity busrecord is
  port (
        AD              : in    std_logic_vector(63 downto 0);
        CBE             : in    std_logic_vector( 7 downto 0);
        PAR             : in    std_logic;
        PAR64           : in    std_logic;
        FRAME_N         : in    std_logic;
        REQ64_N         : in    std_logic;
        TRDY_N          : in    std_logic;
        IRDY_N          : in    std_logic;
        STOP_N          : in    std_logic;
        DEVSEL_N        : in    std_logic;
        ACK64_N         : in    std_logic;
        PERR_N          : in    std_logic;
        SERR_N          : in    std_logic;
        INTR_A          : in    std_logic;
        IDSEL           : in    std_logic;
        REQ_N           : in    std_logic;
        GNT_N           : in    std_logic;
        RST_N           : in    std_logic;
        CLK             : in    std_logic
  );
end busrecord;


architecture get_it_in_writing of busrecord is

  file file_ptr : text is out "waves.tbl";

  begin

  process(CLK)
  variable outline : line;
  begin
    if (CLK'event and CLK = '1') then
      write(outline, AD);
      write(outline, ' ');
      write(outline, CBE);
      write(outline, ' ');
      write(outline, PAR);
      write(outline, ' ');
      write(outline, PAR64);
      write(outline, ' ');
      write(outline, TO_X01(FRAME_N));
      write(outline, ' ');
      write(outline, TO_X01(REQ64_N));
      write(outline, ' ');
      write(outline, TO_X01(TRDY_N));
      write(outline, ' ');
      write(outline, TO_X01(IRDY_N));
      write(outline, ' ');
      write(outline, TO_X01(STOP_N));
      write(outline, ' ');
      write(outline, TO_X01(DEVSEL_N));
      write(outline, ' ');
      write(outline, TO_X01(ACK64_N));
      write(outline, ' ');
      write(outline, TO_X01(PERR_N));
      write(outline, ' ');
      write(outline, TO_X01(SERR_N));
      write(outline, ' ');
      write(outline, TO_X01(INTR_A));
      write(outline, ' ');
      write(outline, TO_X01(IDSEL));
      write(outline, ' ');
      write(outline, TO_X01(REQ_N));
      write(outline, ' ');
      write(outline, TO_X01(GNT_N));
      write(outline, ' ');
      write(outline, NOW);
      writeline(file_ptr, outline);
    end if;
  end process;


end get_it_in_writing;