dumb_arbiter.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 60 行

--------------------------------------------------------------------------
--
--  File:   dumb_arbiter.vhd
--  Rev:    3.0.0
--
--  This is a functional simulation model for a simple arbiter.  This
--  is not synthesizable.  This file is only for simulation.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
--------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity dumb_arbiter is
  port (
        REQ_N           : in    std_logic;
        GNT_N           : out   std_logic;
        SINGLE          : in    std_logic;
        PARK            : in    std_logic;
        CLK             : in    std_logic
        );
end dumb_arbiter;


architecture behave of dumb_arbiter is

  constant TGNT         : time :=  5 ns;

  signal   REQ_N_DELAYED: std_logic := '1';
  signal   GRANT_N      : std_logic := '1';
  signal   ONE_SHOT     : std_logic := '1';

  begin

  process(CLK)
  begin
    if (CLK'event and CLK = '1') then REQ_N_DELAYED <= REQ_N;
    end if;
  end process;

  ONE_SHOT <= REQ_N or ( not REQ_N_DELAYED ) after TGNT;

  process(CLK)
  begin
    if (CLK'event and CLK = '1') then
      if (PARK = '1') then GRANT_N <= '0';
      elsif (SINGLE = '1') then GRANT_N <= ONE_SHOT;
      else GRANT_N <= REQ_N;
      end if;
    end if;
  end process;

  GNT_N <= GRANT_N after TGNT;
 
end behave;