pcim_top.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 420 行 · 第 1/2 页

--------------------------------------------------------------------------
--
--  File:   pcim_top.vhd
--  Rev:    3.0.0
--
--  This is the top-level template file for VHDL designs.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
--------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity pcim_top is
  port (-- PCI ports; do not modify names!
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        IDSEL           : in    std_logic;
        INTR_A          : out   std_logic;
        PERR_N          : inout std_logic;
        SERR_N          : inout std_logic;
        REQ_N           : out   std_logic;
        GNT_N           : in    std_logic;
        RST_N           : in    std_logic;
        PCLK            : in    std_logic;
        -- Add user I/O ports here
        PING_DONE       : out   std_logic;
        PING_REQUEST32  : in    std_logic;
        PING_REQUEST64  : in    std_logic
  );
end pcim_top;


architecture rtl of pcim_top is

  attribute syn_edif_bit_format : string;
  attribute syn_edif_scalar_format : string;
  attribute syn_noclockbuf : boolean;
  attribute syn_hier : string;
  attribute syn_edif_bit_format of rtl : architecture is "%u<%i>";
  attribute syn_edif_scalar_format of rtl : architecture is "%u";
  attribute syn_noclockbuf of rtl : architecture is true;
  attribute syn_hier of rtl : architecture is "hard";

  -- Component declaration of PCI Interface
  component pcim_lc
  port (-- PCI ports; do not modify names!
        AD_IO           : inout std_logic_vector( 63 downto 0);
        CBE_IO          : inout std_logic_vector(  7 downto 0);
        PAR_IO          : inout std_logic;
        PAR64_IO        : inout std_logic;
        FRAME_IO        : inout std_logic;
        REQ64_IO        : inout std_logic;
        TRDY_IO         : inout std_logic;
        IRDY_IO         : inout std_logic;
        STOP_IO         : inout std_logic;
        DEVSEL_IO       : inout std_logic;
        ACK64_IO        : inout std_logic;
        IDSEL_I         : in    std_logic;
        INTA_O          : out   std_logic;
        PERR_IO         : inout std_logic;
        SERR_IO         : inout std_logic;
        REQ_O           : out   std_logic;
        GNT_I           : in    std_logic;
        RST_I           : in    std_logic;
        PCLK            : in    std_logic;
        CFG             : in    std_logic_vector(255 downto 0);
        FRAMEQ_N        : out   std_logic;
        REQ64Q_N        : out   std_logic;
        TRDYQ_N         : out   std_logic;
        IRDYQ_N         : out   std_logic;
        STOPQ_N         : out   std_logic;
        DEVSELQ_N       : out   std_logic;
        ACK64Q_N        : out   std_logic;
        ADDR            : out   std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);
        CFG_VLD         : out   std_logic;
        CFG_HIT         : out   std_logic;
        C_TERM          : in    std_logic;
        C_READY         : in    std_logic;
        ADDR_VLD        : out   std_logic;
        BASE_HIT        : out   std_logic_vector(  7 downto 0);
        S_CYCLE64       : out   std_logic;
        S_TERM          : in    std_logic;
        S_READY         : in    std_logic;
        S_ABORT         : in    std_logic;
        S_WRDN          : out   std_logic;
        S_SRC_EN        : out   std_logic;
        S_DATA_VLD      : out   std_logic;
        S_CBE           : out   std_logic_vector(  7 downto 0);
        PCI_CMD         : out   std_logic_vector( 15 downto 0);
        REQUEST         : in    std_logic;
        REQUEST64       : in    std_logic;
        REQUESTHOLD     : in    std_logic;
        COMPLETE        : in    std_logic;
        M_WRDN          : in    std_logic;
        M_READY         : in    std_logic;
        M_SRC_EN        : out   std_logic;
        M_DATA_VLD      : out   std_logic;
        M_CBE           : in    std_logic_vector(  7 downto 0);
        TIME_OUT        : out   std_logic;
        M_FAIL64        : out   std_logic;
        CFG_SELF        : in    std_logic;
        M_DATA          : out   std_logic;
        DR_BUS          : out   std_logic;
        I_IDLE          : out   std_logic;
        M_ADDR_N        : out   std_logic;
        IDLE            : out   std_logic;
        B_BUSY          : out   std_logic;
        S_DATA          : out   std_logic;
        BACKOFF         : out   std_logic;
        SLOT64          : in    std_logic;
        INTR_N          : in    std_logic;
        PERRQ_N         : out   std_logic;
        SERRQ_N         : out   std_logic;
        KEEPOUT         : in    std_logic;
        CSR             : out   std_logic_vector( 39 downto 0);
        SUB_DATA        : in    std_logic_vector( 31 downto 0);
        RST             : inout std_logic;
        CLK             : inout std_logic
  );
  end component;


  -- Component declaration for Configuration 
  component CFG
  port (
        CFG             : out   std_logic_vector(255 downto 0)
  );
  end component;


  -- Component declaration of Userapp
  component ping64
  port (
        FRAMEQ_N        : in    std_logic;
        REQ64Q_N        : in    std_logic;
        TRDYQ_N         : in    std_logic;
        IRDYQ_N         : in    std_logic;
        STOPQ_N         : in    std_logic;
        DEVSELQ_N       : in    std_logic;
        ACK64Q_N        : in    std_logic;
        ADDR            : in    std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);
        CFG_VLD         : in    std_logic;
        CFG_HIT         : in    std_logic;
        C_TERM          : out   std_logic;
        C_READY         : out   std_logic;
        ADDR_VLD        : in    std_logic;
        BASE_HIT        : in    std_logic_vector(  7 downto 0);
        S_CYCLE64       : in    std_logic;
        S_TERM          : out   std_logic;
        S_READY         : out   std_logic;
        S_ABORT         : out   std_logic;
        S_WRDN          : in    std_logic;
        S_SRC_EN        : in    std_logic;
        S_DATA_VLD      : in    std_logic;
        S_CBE           : in    std_logic_vector(  7 downto 0);
        PCI_CMD         : in    std_logic_vector( 15 downto 0);
        REQUEST         : out   std_logic;
        REQUEST64       : out   std_logic;
        REQUESTHOLD     : out   std_logic;
        COMPLETE        : out   std_logic;
        M_WRDN          : out   std_logic;
        M_READY         : out   std_logic;
        M_SRC_EN        : in    std_logic;
        M_DATA_VLD      : in    std_logic;
        M_CBE           : out   std_logic_vector(  7 downto 0);
        TIME_OUT        : in    std_logic;
        M_FAIL64        : in    std_logic;
        CFG_SELF        : out   std_logic;
        M_DATA          : in    std_logic;
        DR_BUS          : in    std_logic;
        I_IDLE          : in    std_logic;
        M_ADDR_N        : in    std_logic;
        IDLE            : in    std_logic;
        B_BUSY          : in    std_logic;
        S_DATA          : in    std_logic;
        BACKOFF         : in    std_logic;
        SLOT64          : out   std_logic;
        INTR_N          : out   std_logic;
        PERRQ_N         : in    std_logic;
        SERRQ_N         : in    std_logic;
        KEEPOUT         : out   std_logic;
        CSR             : in    std_logic_vector( 39 downto 0);
        SUB_DATA        : out   std_logic_vector( 31 downto 0);
        CFG             : in    std_logic_vector(255 downto 0);
        RST             : in    std_logic;
        CLK             : in    std_logic;
        PING_DONE       : out   std_logic;
        PING_REQUEST32  : in    std_logic;
        PING_REQUEST64  : in    std_logic
  );
  end component;


  -- Internal signals; do not modify names!