ping_tb.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 320 行

----------------------------------------------------------------------------
--
--  File:   ping_tb.vhd
--  Rev:    3.0.0
--
--  This is an example top-level VHDL testbench for the Ping user
--  design.  It instantiates the Ping design, behavioral arbiter and
--  target, and stimulus.  The design of individual components may be
--  customized without affecting the top level.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity ping_tb is 
end ping_tb;


architecture test of ping_tb is

  component dumb_arbiter
  port (
        REQ_N           : in    std_logic;
        GNT_N           : out   std_logic;
        SINGLE          : in    std_logic;
        PARK            : in    std_logic;
        CLK             : in    std_logic
       );
  end component;

  component dumb_target32
  port (
        AD              : inout std_logic_vector(31 downto 0);
        CBE             : inout std_logic_vector( 3 downto 0);
        PAR             : inout std_logic;
        FRAME_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        RST_N           : in    std_logic;
        CLK             : in    std_logic
       );
  end component;

  component dumb_target64
  port (
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        RST_N           : in    std_logic;
        CLK             : in    std_logic
       );
  end component;

  component stimulus
  port (
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        IDSEL           : out   std_logic;
        INTR_A          : in    std_logic;
        PERR_N          : in    std_logic;
        SERR_N          : in    std_logic;
        RST_N           : out   std_logic;
        CLK             : out   std_logic;
        SINGLE          : out   std_logic;
        PARK            : out   std_logic;
        PING_DONE       : in    std_logic;
        PING_REQUEST32  : out   std_logic;
        PING_REQUEST64  : out   std_logic
       );
  end component;

  component pcim_top
  port (
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        IDSEL           : in    std_logic;
        INTR_A          : out   std_logic;
        PERR_N          : inout std_logic;
        SERR_N          : inout std_logic;
        REQ_N           : out   std_logic;
        GNT_N           : in    std_logic;
        RST_N           : in    std_logic;
        PCLK            : in    std_logic;
        PING_DONE       : out   std_logic;
        PING_REQUEST32  : in    std_logic;
        PING_REQUEST64  : in    std_logic
       );
  end component;

  component busrecord
  port (
        AD              : in    std_logic_vector(63 downto 0);
        CBE             : in    std_logic_vector( 7 downto 0);
        PAR             : in    std_logic;
        PAR64           : in    std_logic;
        FRAME_N         : in    std_logic;
        REQ64_N         : in    std_logic;
        TRDY_N          : in    std_logic;
        IRDY_N          : in    std_logic;
        STOP_N          : in    std_logic;
        DEVSEL_N        : in    std_logic;
        ACK64_N         : in    std_logic;
        PERR_N          : in    std_logic;
        SERR_N          : in    std_logic;
        INTR_A          : in    std_logic;
        IDSEL           : in    std_logic;
        REQ_N           : in    std_logic;
        GNT_N           : in    std_logic;
        RST_N           : in    std_logic;
        CLK             : in    std_logic
       );
  end component;


  -- Top level interconnect

  signal AD             : std_logic_vector(63 downto 0);
  signal CBE            : std_logic_vector( 7 downto 0);
  signal PAR            : std_logic;
  signal PAR64          : std_logic;
  signal FRAME_N        : std_logic;
  signal REQ64_N        : std_logic;
  signal TRDY_N         : std_logic;
  signal IRDY_N         : std_logic;
  signal STOP_N         : std_logic;
  signal DEVSEL_N       : std_logic;
  signal ACK64_N        : std_logic;
  signal IDSEL          : std_logic;
  signal INTR_A         : std_logic;
  signal PERR_N         : std_logic;
  signal SERR_N         : std_logic;
  signal REQ_N          : std_logic;
  signal GNT_N          : std_logic;
  signal RST_N          : std_logic;
  signal CLK            : std_logic;

  signal SINGLE         : std_logic;
  signal PARK           : std_logic;
  signal PING_DONE      : std_logic;
  signal PING_REQUEST32 : std_logic;
  signal PING_REQUEST64 : std_logic;

  
begin

  ARB : dumb_arbiter port map(
    REQ_N               => REQ_N,
    GNT_N               => GNT_N,
    SINGLE              => SINGLE,
    PARK                => PARK,
    CLK                 => CLK
    );

  TRG32 : dumb_target32 port map(
    AD                  => AD(31 downto 0),
    CBE                 => CBE(3 downto 0),
    PAR                 => PAR,
    FRAME_N             => FRAME_N,
    TRDY_N              => TRDY_N,
    IRDY_N              => IRDY_N,
    STOP_N              => STOP_N,
    DEVSEL_N            => DEVSEL_N,
    RST_N               => RST_N,
    CLK                 => CLK
    );

  TRG64 : dumb_target64 port map(
    AD                  => AD,
    CBE                 => CBE,
    PAR                 => PAR,
    PAR64               => PAR64,
    FRAME_N             => FRAME_N,
    REQ64_N             => REQ64_N,
    TRDY_N              => TRDY_N,
    IRDY_N              => IRDY_N,
    STOP_N              => STOP_N,
    DEVSEL_N            => DEVSEL_N,
    ACK64_N             => ACK64_N,
    RST_N               => RST_N,
    CLK                 => CLK
    );

  STM : stimulus port map(
    AD                  => AD,
    CBE                 => CBE,
    PAR                 => PAR,
    PAR64               => PAR64,
    FRAME_N             => FRAME_N,
    REQ64_N             => REQ64_N,
    TRDY_N              => TRDY_N,
    IRDY_N              => IRDY_N,
    STOP_N              => STOP_N,
    DEVSEL_N            => DEVSEL_N,
    ACK64_N             => ACK64_N,
    IDSEL               => IDSEL,
    INTR_A              => INTR_A,
    PERR_N              => PERR_N,
    SERR_N              => SERR_N,
    RST_N               => RST_N,
    CLK                 => CLK,
    SINGLE              => SINGLE,
    PARK                => PARK,
    PING_DONE           => PING_DONE,
    PING_REQUEST32      => PING_REQUEST32,
    PING_REQUEST64      => PING_REQUEST64
    ); 

  UUT : pcim_top port map(
    AD                  => AD,
    CBE                 => CBE,
    PAR                 => PAR,
    PAR64               => PAR64,
    FRAME_N             => FRAME_N,
    REQ64_N             => REQ64_N,
    TRDY_N              => TRDY_N,
    IRDY_N              => IRDY_N,
    STOP_N              => STOP_N,
    DEVSEL_N            => DEVSEL_N,
    ACK64_N             => ACK64_N,
    IDSEL               => IDSEL,
    INTR_A              => INTR_A,
    PERR_N              => PERR_N,
    SERR_N              => SERR_N,
    REQ_N               => REQ_N,
    GNT_N               => GNT_N,
    RST_N               => RST_N,
    PCLK                => CLK,
    PING_DONE           => PING_DONE,
    PING_REQUEST32      => PING_REQUEST32,
    PING_REQUEST64      => PING_REQUEST64
    );

  REC : busrecord port map(
    AD                  => AD,
    CBE                 => CBE,
    PAR                 => PAR,
    PAR64               => PAR64,
    FRAME_N             => FRAME_N,
    REQ64_N             => REQ64_N,
    TRDY_N              => TRDY_N,
    IRDY_N              => IRDY_N,
    STOP_N              => STOP_N,
    DEVSEL_N            => DEVSEL_N,
    ACK64_N             => ACK64_N,
    IDSEL               => IDSEL,
    INTR_A              => INTR_A,
    PERR_N              => PERR_N,
    SERR_N              => SERR_N,
    REQ_N               => REQ_N,
    GNT_N               => GNT_N,
    RST_N               => RST_N,
    CLK                 => CLK
    );


  -- Pull ups on bus

  FRAME_N <= 'H';
  REQ64_N <= 'H';
  TRDY_N <= 'H';
  IRDY_N <= 'H';
  STOP_N <= 'H';
  DEVSEL_N <= 'H';
  ACK64_N <= 'H';
  INTR_A <= 'H';
  PERR_N <= 'H';
  SERR_N <= 'H';
  REQ_N <= 'H';
  GNT_N <= 'H';
 
  -- Extension pull ups

  PAR64 <= 'H';
  CBE(7 downto 4) <= (others => 'H');
  AD(63 downto 32) <= (others => 'H');


end test;


configuration cfg_ping_tb of ping_tb is
for test
end for;
end cfg_ping_tb;