userapp.vhd

来自「xilinx官方PCIcore 有详细说明文档」· VHDL 代码 · 共 104 行

----------------------------------------------------------------------------
--
--  File:   userapp.vhd
--  Rev:    3.0.0
--
--  This is an example template for the user backend application.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
----------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;


entity userapp is
  port (-- Interface to PCI Logicore.
        FRAMEQ_N        : in    std_logic;
        REQ64Q_N        : in    std_logic;
        TRDYQ_N         : in    std_logic;
        IRDYQ_N         : in    std_logic;
        STOPQ_N         : in    std_logic;
        DEVSELQ_N       : in    std_logic;
        ACK64Q_N        : in    std_logic;

        ADDR            : in    std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);

        CFG_VLD         : in    std_logic;
        CFG_HIT         : in    std_logic;
        C_TERM          : out   std_logic;
        C_READY         : out   std_logic;

        ADDR_VLD        : in    std_logic;
        BASE_HIT        : in    std_logic_vector(  7 downto 0);

        S_CYCLE64       : in    std_logic;
        S_TERM          : out   std_logic;
        S_READY         : out   std_logic;
        S_ABORT         : out   std_logic;
        S_WRDN          : in    std_logic;
        S_SRC_EN        : in    std_logic;
        S_DATA_VLD      : in    std_logic;
        S_CBE           : in    std_logic_vector(  7 downto 0);
        PCI_CMD         : in    std_logic_vector( 15 downto 0);

        REQUEST         : out   std_logic;
        REQUEST64       : out   std_logic;
        REQUESTHOLD     : out   std_logic;
        COMPLETE        : out   std_logic;

        M_WRDN          : out   std_logic;
        M_READY         : out   std_logic;
        M_SRC_EN        : in    std_logic;
        M_DATA_VLD      : in    std_logic;
        M_CBE           : out   std_logic_vector(  7 downto 0);

        TIME_OUT        : in    std_logic;
        M_FAIL64        : in    std_logic;
        CFG_SELF        : out   std_logic;

        M_DATA          : in    std_logic;
        DR_BUS          : in    std_logic;
        I_IDLE          : in    std_logic;
        M_ADDR_N        : in    std_logic;
        IDLE            : in    std_logic;
        B_BUSY          : in    std_logic;
        S_DATA          : in    std_logic;
        BACKOFF         : in    std_logic;

        SLOT64          : out   std_logic;
        INTR_N          : out   std_logic;
        PERRQ_N         : in    std_logic;
        SERRQ_N         : in    std_logic;
        KEEPOUT         : out   std_logic;

        CSR             : in    std_logic_vector( 39 downto 0);
        SUB_DATA        : out   std_logic_vector( 31 downto 0);
        CFG             : in    std_logic_vector(255 downto 0);

        RST             : in    std_logic;
        CLK             : in    std_logic
  );
end userapp;


architecture rtl of userapp is

  attribute syn_edif_bit_format : string;
  attribute syn_edif_scalar_format : string;
  attribute syn_noclockbuf : boolean;
  attribute syn_hier : string;
  attribute syn_edif_bit_format of rtl : architecture is "%u<%i>";
  attribute syn_edif_scalar_format of rtl : architecture is "%u";
  attribute syn_noclockbuf of rtl : architecture is true;
  attribute syn_hier of rtl : architecture is "hard";

begin
  -- Add user application here.
end rtl;