pcim_top.vhd

xilinx官方PCIcore 有详细说明文档

--------------------------------------------------------------------------
--
--  File:   pcim_top.vhd
--  Rev:    3.0.0
--
--  This is the top-level template file for VHDL designs.
--  The user should place his backend application design in the
--  userapp module.
--
--  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.
--
--------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity pcim_top is
  port (-- PCI ports; do not modify names!
        AD              : inout std_logic_vector(63 downto 0);
        CBE             : inout std_logic_vector( 7 downto 0);
        PAR             : inout std_logic;
        PAR64           : inout std_logic;
        FRAME_N         : inout std_logic;
        REQ64_N         : inout std_logic;
        TRDY_N          : inout std_logic;
        IRDY_N          : inout std_logic;
        STOP_N          : inout std_logic;
        DEVSEL_N        : inout std_logic;
        ACK64_N         : inout std_logic;
        IDSEL           : in    std_logic;
        INTR_A          : out   std_logic;
        PERR_N          : inout std_logic;
        SERR_N          : inout std_logic;
        REQ_N           : out   std_logic;
        GNT_N           : in    std_logic;
        RST_N           : in    std_logic;
        PCLK            : in    std_logic
        -- Add user I/O ports here
  );
end pcim_top;


architecture rtl of pcim_top is

  attribute syn_edif_bit_format : string;
  attribute syn_edif_scalar_format : string;
  attribute syn_noclockbuf : boolean;
  attribute syn_hier : string;
  attribute syn_edif_bit_format of rtl : architecture is "%u<%i>";
  attribute syn_edif_scalar_format of rtl : architecture is "%u";
  attribute syn_noclockbuf of rtl : architecture is true;
  attribute syn_hier of rtl : architecture is "hard";

  -- Component declaration of PCI Interface
  component pcim_lc
  port (-- PCI ports; do not modify names!
        AD_IO           : inout std_logic_vector( 63 downto 0);
        CBE_IO          : inout std_logic_vector(  7 downto 0);
        PAR_IO          : inout std_logic;
        PAR64_IO        : inout std_logic;
        FRAME_IO        : inout std_logic;
        REQ64_IO        : inout std_logic;
        TRDY_IO         : inout std_logic;
        IRDY_IO         : inout std_logic;
        STOP_IO         : inout std_logic;
        DEVSEL_IO       : inout std_logic;
        ACK64_IO        : inout std_logic;
        IDSEL_I         : in    std_logic;
        INTA_O          : out   std_logic;
        PERR_IO         : inout std_logic;
        SERR_IO         : inout std_logic;
        REQ_O           : out   std_logic;
        GNT_I           : in    std_logic;
        RST_I           : in    std_logic;
        PCLK            : in    std_logic;
        CFG             : in    std_logic_vector(255 downto 0);
        FRAMEQ_N        : out   std_logic;
        REQ64Q_N        : out   std_logic;
        TRDYQ_N         : out   std_logic;
        IRDYQ_N         : out   std_logic;
        STOPQ_N         : out   std_logic;
        DEVSELQ_N       : out   std_logic;
        ACK64Q_N        : out   std_logic;
        ADDR            : out   std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);
        CFG_VLD         : out   std_logic;
        CFG_HIT         : out   std_logic;
        C_TERM          : in    std_logic;
        C_READY         : in    std_logic;
        ADDR_VLD        : out   std_logic;
        BASE_HIT        : out   std_logic_vector(  7 downto 0);
        S_CYCLE64       : out   std_logic;
        S_TERM          : in    std_logic;
        S_READY         : in    std_logic;
        S_ABORT         : in    std_logic;
        S_WRDN          : out   std_logic;
        S_SRC_EN        : out   std_logic;
        S_DATA_VLD      : out   std_logic;
        S_CBE           : out   std_logic_vector(  7 downto 0);
        PCI_CMD         : out   std_logic_vector( 15 downto 0);
        REQUEST         : in    std_logic;
        REQUEST64       : in    std_logic;
        REQUESTHOLD     : in    std_logic;
        COMPLETE        : in    std_logic;
        M_WRDN          : in    std_logic;
        M_READY         : in    std_logic;
        M_SRC_EN        : out   std_logic;
        M_DATA_VLD      : out   std_logic;
        M_CBE           : in    std_logic_vector(  7 downto 0);
        TIME_OUT        : out   std_logic;
        M_FAIL64        : out   std_logic;
        CFG_SELF        : in    std_logic;
        M_DATA          : out   std_logic;
        DR_BUS          : out   std_logic;
        I_IDLE          : out   std_logic;
        M_ADDR_N        : out   std_logic;
        IDLE            : out   std_logic;
        B_BUSY          : out   std_logic;
        S_DATA          : out   std_logic;
        BACKOFF         : out   std_logic;
        SLOT64          : in    std_logic;
        INTR_N          : in    std_logic;
        PERRQ_N         : out   std_logic;
        SERRQ_N         : out   std_logic;
        KEEPOUT         : in    std_logic;
        CSR             : out   std_logic_vector( 39 downto 0);
        SUB_DATA        : in    std_logic_vector( 31 downto 0);
        RST             : inout std_logic;
        CLK             : inout std_logic
  );
  end component;

  -- Component declaration for Configuration 
  component CFG
  port (
        CFG             : out   std_logic_vector(255 downto 0)
  );
  end component;


  -- Component declaration of Userapp
  component userapp
  port (
        FRAMEQ_N        : in    std_logic;
        REQ64Q_N        : in    std_logic;
        TRDYQ_N         : in    std_logic;
        IRDYQ_N         : in    std_logic;
        STOPQ_N         : in    std_logic;
        DEVSELQ_N       : in    std_logic;
        ACK64Q_N        : in    std_logic;
        ADDR            : in    std_logic_vector( 31 downto 0);
        ADIO            : inout std_logic_vector( 63 downto 0);
        CFG_VLD         : in    std_logic;
        CFG_HIT         : in    std_logic;
        C_TERM          : out   std_logic;
        C_READY         : out   std_logic;
        ADDR_VLD        : in    std_logic;
        BASE_HIT        : in    std_logic_vector(  7 downto 0);
        S_CYCLE64       : in    std_logic;
        S_TERM          : out   std_logic;
        S_READY         : out   std_logic;
        S_ABORT         : out   std_logic;
        S_WRDN          : in    std_logic;
        S_SRC_EN        : in    std_logic;
        S_DATA_VLD      : in    std_logic;
        S_CBE           : in    std_logic_vector(  7 downto 0);
        PCI_CMD         : in    std_logic_vector( 15 downto 0);
        REQUEST         : out   std_logic;
        REQUEST64       : out   std_logic;
        REQUESTHOLD     : out   std_logic;
        COMPLETE        : out   std_logic;
        M_WRDN          : out   std_logic;
        M_READY         : out   std_logic;
        M_SRC_EN        : in    std_logic;
        M_DATA_VLD      : in    std_logic;
        M_CBE           : out   std_logic_vector(  7 downto 0);
        TIME_OUT        : in    std_logic;
        M_FAIL64        : in    std_logic;
        CFG_SELF        : out   std_logic;
        M_DATA          : in    std_logic;
        DR_BUS          : in    std_logic;
        I_IDLE          : in    std_logic;
        M_ADDR_N        : in    std_logic;
        IDLE            : in    std_logic;
        B_BUSY          : in    std_logic;
        S_DATA          : in    std_logic;
        BACKOFF         : in    std_logic;
        SLOT64          : out   std_logic;
        INTR_N          : out   std_logic;
        PERRQ_N         : in    std_logic;
        SERRQ_N         : in    std_logic;
        KEEPOUT         : out   std_logic;
        CSR             : in    std_logic_vector( 39 downto 0);
        SUB_DATA        : out   std_logic_vector( 31 downto 0);
        CFG             : in    std_logic_vector(255 downto 0);
        RST             : in    std_logic;
        CLK             : in    std_logic
  );
  end component;


  -- Internal signals; do not modify names!

  signal FRAMEQ_N       : std_logic;
  signal REQ64Q_N       : std_logic;
  signal TRDYQ_N        : std_logic;
  signal IRDYQ_N        : std_logic;
  signal STOPQ_N        : std_logic;
  signal DEVSELQ_N      : std_logic;
  signal ACK64Q_N       : std_logic;
  signal ADDR           : std_logic_vector( 31 downto 0);
  signal ADIO           : std_logic_vector( 63 downto 0);
  signal CFG_VLD        : std_logic;
  signal CFG_HIT        : std_logic;
  signal C_TERM         : std_logic;
  signal C_READY        : std_logic;
  signal ADDR_VLD       : std_logic;
  signal BASE_HIT       : std_logic_vector(  7 downto 0);
  signal S_CYCLE64      : std_logic;
  signal S_TERM         : std_logic;
  signal S_READY        : std_logic;
  signal S_ABORT        : std_logic;
  signal S_WRDN         : std_logic;
  signal S_SRC_EN       : std_logic;
  signal S_DATA_VLD     : std_logic;
  signal S_CBE          : std_logic_vector(  7 downto 0);
  signal PCI_CMD        : std_logic_vector( 15 downto 0);
  signal REQUEST        : std_logic;
  signal REQUEST64      : std_logic;
  signal REQUESTHOLD    : std_logic;
  signal COMPLETE       : std_logic;
  signal M_WRDN         : std_logic;
  signal M_READY        : std_logic;
  signal M_SRC_EN       : std_logic;
  signal M_DATA_VLD     : std_logic;
  signal M_CBE          : std_logic_vector(  7 downto 0);
  signal TIME_OUT       : std_logic;
  signal M_FAIL64       : std_logic;
  signal CFG_SELF       : std_logic;
  signal M_DATA         : std_logic;
  signal DR_BUS         : std_logic;
  signal I_IDLE         : std_logic;
  signal M_ADDR_N       : std_logic;
  signal IDLE           : std_logic;
  signal B_BUSY         : std_logic;
  signal S_DATA         : std_logic;
  signal BACKOFF        : std_logic;
  signal SLOT64         : std_logic;
  signal INTR_N         : std_logic;
  signal PERRQ_N        : std_logic;
  signal SERRQ_N        : std_logic;
  signal KEEPOUT        : std_logic;
  signal CSR            : std_logic_vector( 39 downto 0);
  signal SUB_DATA       : std_logic_vector( 31 downto 0);
  signal CFG_BUS        : std_logic_vector(255 downto 0);
  signal RST            : std_logic;
  signal CLK            : std_logic;


begin


  -- Do not modify any port, signal, or instance
  -- names related to the PCI Interface!

  PCI_CORE : pcim_lc port map (
    AD_IO               => AD,
    CBE_IO              => CBE,
    PAR_IO              => PAR,
    PAR64_IO            => PAR64,
    FRAME_IO            => FRAME_N,
    REQ64_IO            => REQ64_N,
    TRDY_IO             => TRDY_N,
    IRDY_IO             => IRDY_N,
    STOP_IO             => STOP_N,
    DEVSEL_IO           => DEVSEL_N,
    ACK64_IO            => ACK64_N,
    IDSEL_I             => IDSEL,
    INTA_O              => INTR_A,
    PERR_IO             => PERR_N,
    SERR_IO             => SERR_N,
    REQ_O               => REQ_N,
    GNT_I               => GNT_N,
    RST_I               => RST_N,
    PCLK                => PCLK,

    FRAMEQ_N            => FRAMEQ_N,
    REQ64Q_N            => REQ64Q_N,
    TRDYQ_N             => TRDYQ_N,
    IRDYQ_N             => IRDYQ_N,
    STOPQ_N             => STOPQ_N,
    DEVSELQ_N           => DEVSELQ_N,
    ACK64Q_N            => ACK64Q_N,
    ADDR                => ADDR,
    ADIO                => ADIO,
    CFG_VLD             => CFG_VLD,
    CFG_HIT             => CFG_HIT,
    C_TERM              => C_TERM,
    C_READY             => C_READY,
    ADDR_VLD            => ADDR_VLD,
    BASE_HIT            => BASE_HIT,
    S_CYCLE64           => S_CYCLE64,
    S_TERM              => S_TERM,
    S_READY             => S_READY,
    S_ABORT             => S_ABORT,
    S_WRDN              => S_WRDN,
    S_SRC_EN            => S_SRC_EN,
    S_DATA_VLD          => S_DATA_VLD,
    S_CBE               => S_CBE,
    PCI_CMD             => PCI_CMD,
    REQUEST             => REQUEST,
    REQUEST64           => REQUEST64,
    REQUESTHOLD         => REQUESTHOLD,
    COMPLETE            => COMPLETE,
    M_WRDN              => M_WRDN,
    M_READY             => M_READY,
    M_SRC_EN            => M_SRC_EN,
    M_DATA_VLD          => M_DATA_VLD,
    M_CBE               => M_CBE,
    TIME_OUT            => TIME_OUT,
    M_FAIL64            => M_FAIL64,
    CFG_SELF            => CFG_SELF,
    M_DATA              => M_DATA,
    DR_BUS              => DR_BUS,
    I_IDLE              => I_IDLE,
    M_ADDR_N            => M_ADDR_N,
    IDLE                => IDLE,
    B_BUSY              => B_BUSY,
    S_DATA              => S_DATA,
    BACKOFF             => BACKOFF,
    SLOT64              => SLOT64,
    INTR_N              => INTR_N,
    PERRQ_N             => PERRQ_N,
    SERRQ_N             => SERRQ_N,
    KEEPOUT             => KEEPOUT,
    CSR                 => CSR,
    SUB_DATA            => SUB_DATA,
    CFG                 => CFG_BUS,
    RST                 => RST,
    CLK                 => CLK
  );


  -- Instantiate the configuration module

  CFG_INST : CFG port map (CFG => CFG_BUS);


  -- Instantiate the user application

  USER_APP : userapp port map (
    FRAMEQ_N            => FRAMEQ_N,
    REQ64Q_N            => REQ64Q_N,
    TRDYQ_N             => TRDYQ_N,
    IRDYQ_N             => IRDYQ_N,
    STOPQ_N             => STOPQ_N,
    DEVSELQ_N           => DEVSELQ_N,
    ACK64Q_N            => ACK64Q_N,
    ADDR                => ADDR,
    ADIO                => ADIO,
    CFG_VLD             => CFG_VLD,
    CFG_HIT             => CFG_HIT,
    C_TERM              => C_TERM,
    C_READY             => C_READY,
    ADDR_VLD            => ADDR_VLD,
    BASE_HIT            => BASE_HIT,
    S_CYCLE64           => S_CYCLE64,
    S_TERM              => S_TERM,
    S_READY             => S_READY,
    S_ABORT             => S_ABORT,
    S_WRDN              => S_WRDN,
    S_SRC_EN            => S_SRC_EN,
    S_DATA_VLD          => S_DATA_VLD,
    S_CBE               => S_CBE,
    PCI_CMD             => PCI_CMD,
    REQUEST             => REQUEST,
    REQUEST64           => REQUEST64,
    REQUESTHOLD         => REQUESTHOLD,
    COMPLETE            => COMPLETE,
    M_WRDN              => M_WRDN,
    M_READY             => M_READY,
    M_SRC_EN            => M_SRC_EN,
    M_DATA_VLD          => M_DATA_VLD,
    M_CBE               => M_CBE,
    TIME_OUT            => TIME_OUT,
    M_FAIL64            => M_FAIL64,
    CFG_SELF            => CFG_SELF,
    M_DATA              => M_DATA,
    DR_BUS              => DR_BUS,
    I_IDLE              => I_IDLE,
    M_ADDR_N            => M_ADDR_N,
    IDLE                => IDLE,
    B_BUSY              => B_BUSY,
    S_DATA              => S_DATA,
    BACKOFF             => BACKOFF,
    SLOT64              => SLOT64,
    INTR_N              => INTR_N,
    PERRQ_N             => PERRQ_N,
    SERRQ_N             => SERRQ_N,
    KEEPOUT             => KEEPOUT,
    CSR                 => CSR,
    SUB_DATA            => SUB_DATA,
    CFG                 => CFG_BUS,
    RST                 => RST,
    CLK                 => CLK
  );


end rtl;