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ping.traces </tt>
<br><tt>
ping.wfc </tt>
<br><tt>
run_ping</tt>
<br><tt> xilinx/</tt>
<br><tt>
README</tt>
<br><tt>
run_xilinx</tt>
<br><tt>
run_xilinx.bat</tt>
<br><tt> post_sim/</tt>
<br><tt>
.synopsys_vss.setup </tt>
<br><tt>
README</tt>
<br><tt>
analyze_ping </tt>
<br><tt>
modelsim.do</tt>
<br><tt>
ping.files </tt>
<br><tt>
ping.include </tt>
<br><tt>
ping.traces </tt>
<br><tt>
ping.wfc </tt>
<br><tt>
run_ping </tt>
<br><tt> source/</tt>
<br><tt>
README</tt>
<br><tt>
busrecord.vhd</tt>
<br><tt>
cfg_ping.vhd</tt>
<br><tt>
dumb_arbiter.vhd</tt>
<br><tt>
dumb_targ32.vhd</tt>
<br><tt>
dumb_targ64.vhd</tt>
<br><tt>
pcim_top.vhd</tt>
<br><tt>
ping.vhd</tt>
<br><tt>
ping_tb.vhd</tt>
<br><tt>
stimulus.vhd</tt>
<br><tt> synthesis/</tt>
<br><tt>
.synopsys_dc.setup</tt>
<br><tt>
README</tt>
<br><tt>
WORK/</tt>
<br><tt>
leonardo.tcl</tt>
<br><tt>
run_xst.bat</tt>
<br><tt>
run_xst.cmd</tt>
<br><tt>
run_xst.csh</tt>
<br><tt>
run_xst.prj</tt>
<br><tt>
synopsys.dc</tt>
<br><tt> src/</tt>
<br><tt> README</tt>
<br><tt> guide/</tt>
<br><tt>
README</tt>
<br><tt>
2s150fg456_64_66.ncd</tt>
<br><tt>
2s200fg456_64_66.ncd</tt>
<br><tt>
2s300efg456_64_66.ncd</tt>
<br><tt>
2v1000fg456_64_66.ncd</tt>
<br><tt>
v300bg432_64_66.ncd</tt>
<br><tt>
v300ebg432_64_66.ncd</tt>
<br><tt>
v1000fg680_64_66.ncd</tt>
<br><tt>
v1000efg680_64_66.ncd</tt>
<br><tt> ucf/</tt>
<br><tt>
README</tt>
<br><tt>
2s100fg456_64_33.ucf</tt>
<br><tt>
2s150fg456_64_33.ucf</tt>
<br><tt>
2s150fg456_64_66.ucf</tt>
<br><tt>
2s200fg456_64_33.ucf</tt>
<br><tt>
2s200fg456_64_66.ucf</tt>
<br><tt>
2s100efg456_64_33.ucf</tt>
<br><tt>
2s150efg456_64_33.ucf</tt>
<br><tt>
2s200efg456_64_33.ucf</tt>
<br><tt>
2s300efg456_64_33.ucf</tt>
<br><tt>
2s300efg456_64_66.ucf</tt>
<br><tt>
3s1000fg456_64_33.ucf</tt>
<br><tt>
2v1000fg456_64_33.ucf</tt>
<br><tt>
2v1000fg456_64_66.ucf</tt>
<br><tt>
2vp7ff672_64_33.ucf</tt>
<br><tt>
2vp7ff672_64_66.ucf</tt>
<br><tt>
v100ebg352_64_33.ucf</tt>
<br><tt>
v300bg432_64_33.ucf</tt>
<br><tt>
v300bg432_64_66.ucf</tt>
<br><tt>
v300ebg432_64_33.ucf</tt>
<br><tt>
v300ebg432_64_66.ucf</tt>
<br><tt>
v1000fg680_64_33.ucf</tt>
<br><tt>
v1000fg680_64_66.ucf</tt>
<br><tt>
v1000efg680_64_33.ucf</tt>
<br><tt>
v1000efg680_64_66.ucf</tt>
<br><tt> wrap/</tt>
<br><tt>
README</tt>
<br><tt>
pcim_lc_33_3_s.vhd</tt>
<br><tt>
pcim_lc_33_5_s.vhd</tt>
<br><tt>
pcim_lc_66_3_d.vhd</tt>
<br><tt>
pcim_lc_66_3_s.vhd</tt>
<br><tt> xpci/</tt>
<br><tt>
README</tt>
<br><tt>
cfg.vhd</tt>
<br><tt>
pci_lc_i.ngo</tt>
<br><tt>
pci_lc_i.vhd</tt>
<br><tt>
pcim_lc.vhd</tt>
<br><tt>
pcim_top.vhd</tt>
<br><tt>
userapp.vhd</tt>
<p>For more details on the LogiCORE PCI64 interface, see the following
documents included in the docs/ sub-directory of your download.
<ul>
<li>
<i>LogiCORE PCI Design Guide v3.0</i></li>
<li>
<i>LogiCORE PCI Implementation Guide</i></li>
</ul>
Also consult the <i>PCI Systems Architecture</i> text by Mindshare and
the <i>PCI Local Bus Specification, Revision 2.3</i>.
<h3>
1.3. <a NAME="Maintenance"></a>Maintenance</h3>
This product comes with one year of maintenance from the original purchase
date; you are entitled to receive major product and documentation updates
during that time.
<h3>
1.4. <a NAME="Support"></a>Support</h3>
This product comes with free technical and product information telephone
support (toll free in the U.S. and Canada). You can also fax or email
your questions.
<p>The fastest method for obtaining LogiCORE PCI64 interface technical
support is through the <a href="http://support.xilinx.com">support.xilinx.com</a>
web page. Your inquiry is routed to a team of engineers with specific
expertise in using the LogiCORE PCI64 interface.
<p>Xilinx provides technical support for use of the LogiCORE PCI64 interface
product as described in the <i>LogiCORE PCI Design Guide</i> and the <i>LogiCORE
PCI Implementation Guide</i>. Xilinx cannot guarantee timing, functionality,
or support of the LogiCORE PCI64 interface product if designs are implemented
in unsupported devices or if the product is customized beyond what is allowed
in the <i>LogiCORE PCI Design Guide</i>.
<h4>
<a href="#Release Notes">Back to Top</a></h4>
</td>
</tr>
</table>
<table COLS=1 WIDTH="596" >
<tr>
<td>
<h2>
2.0. <a NAME="Installation"></a>Installation</h2>
This section explains the system requirements and how to install the LogiCORE
PCI64 interface after downloading it from the web based configuration and
download tool.
<h3>
2.1. <a NAME="System Requirements"></a>System Requirements</h3>
In order to use the LogiCORE PCI64 interface, you must verify that your
computing platform is capable of running the required design tools.
Consult the documentation shipped with your design tools to verify that
your computing platform is sufficient.
<p>The LogiCORE PCI64 interface requires the use of either Xilinx Alliance
Xilinx Foundation tools, version 5.2i Service Pack 2. Various third
party synthesis and simulation tools are supported. These may be
selected "a la carte" from the list below:
<p><b>Verilog Design Flow:</b>
<ul>Supported Synthesis Tools
<ul>
<li>
Synopsys FPGA Compiler, v1999.10</li>
<li>
Synopsys FPGA Express, v2000</li>
<li>
Synplicity Synplify, v6.2</li>
<li>
Exemplar LeonardoSpectrum, v2000</li>
<li>
Xilinx XST</li>
</ul>
Supported Simulation Tools
<ul>
<li>
Cadence Verilog-XL, v3.0</li>
<li>
Model Technology ModelSim, v5.5b</li>
</ul>
</ul>
<b>VHDL Design Flow:</b>
<ul>Supported Synthesis Tools
<ul>
<li>
Synopsys FPGA Compiler, v1999.10</li>
<li>
Synopsys FPGA Express, v2000</li>
<li>
Synplicity Synplify, v6.2</li>
<li>
Exemplar LeonardoSpectrum, v2000</li>
<li>
Xilinx XST</li>
</ul>
Supported Simulation Tools
<ul>
<li>
Synopsys Vss, v1999.10</li>
<li>
Model Technology ModelSim, v5.5b</li>
</ul>
</ul>
Additionally, you must have approximately 20 Mbytes of free disk space
available.
<h3>
2.2. <a NAME="Unpacking Files"></a>Unpacking Files</h3>
During configuration and download, a selection is made between ZIP format
and GZ format for the download. The contents of the ZIP file and
the GZ file are identical.
<p>If you have downloaded the customPciCore.zip file, then you can use
any unzip utility to decompress and extract the files. Suitable tools
include "unzip" on UNIX workstations, and "winzip" on Microsoft Windows
platforms.
<p>If you have downloaded the customPciCore.tar.gz file, you must first
decompress the file using the GNU "gunzip" utility. After decompressing
the file, extract the files from the TAR archive using the command "tar
xvf customPciCore.tar". These utilities are readily available on
UNIX workstations. For ease of use, users of Microsoft Windows should
download the ZIP file instead of the GZ format file.
<p>Make a cursory comparison of the resulting directories and files to
the list presented in the <a href="#Software">Software</a> section to make
sure you received the files you expected.
<h4>
<a href="#Release Notes">Back to Top</a></h4>
</td>
</tr>
</table>
<table COLS=1 WIDTH="596" >
<tr>
<td>
<h2>
3.0. <a NAME="Known Issues"></a>Known Issues</h2>
This is a list of known issues. Please read this entire section so that
you are aware of any late breaking information.
<h3>
3.1. <a NAME="Functional Simulation"></a>Functional Simulation</h3>
None.
<h3>
3.2. <a NAME="Synthesis"></a>Synthesis</h3>
None.
<h3>
3.3. <a NAME="Implementation"></a>Implementation</h3>
The design files present in this release are based on timing parameters
from, and intended for use with, the speedfiles shipped with the supported
tools. As more device characterization data is collected, Xilinx may
update the speedfiles to more closely model device operation.
<p>Xilinx reserves the right to modify the design files, including the
PCI interface pinout, in order to maintain full PCI compliance after speedfile
updates occur. To the full extent possible, Xilinx will incorporate
such modifications without using pinout changes in an effort to provide
"transparent" design file updates.
<p>For some 66 MHz designs, bitgen must be run with a special option to
change the behavior of a global clock buffer used in the design.
When you are ready to generate a bitstream for a 66 MHz design, run bitgen
with the following option:
<ul><tt>bitgen -g Gclkdel3:11111 pcim_top_routed.ncd [XCV300-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel3:01111 pcim_top_routed.ncd [XCV1000-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel3:00101 pcim_top_routed.ncd [XCV300E-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel3:01111 pcim_top_routed.ncd [XCV1000E-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel2:00110 pcim_top_routed.ncd [XC2S150-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel2:00111 pcim_top_routed.ncd [XC2S200-6]</tt></ul>
<ul><tt>bitgen -g Gclkdel2:00101 pcim_top_routed.ncd [XC2S300E-6]</tt></ul>
This option is used to introduce additional delay on a global clock net.
For 66 MHz designs, it is important to note that this additional delay
is observable on the CLK output of the LogiCORE PCI64 interface, which
is supplied to the user application. Timing constraints for the user
application must be generated with this in mind. The place and route
tools are not aware of this additional delay because it is added as a bitstream
post-processing step. Consult the user constraint file for examples
of how to account for this delay when generating timing specifications.
<p>This option <u>must not be used</u> for Virtex-II designs.
<p>This option <u>must not be used</u> for 33 MHz designs.
<p>Various warnings may be issued by the Xilinx tools. However,
no errors should occur.
<p>The UCF files for some Virtex-II implementations may have pin placement
constraints which use preferred global clock input pins for non-clock
PCI signals. For some applications, this can be problematic if these
special pin locations could be better used for clock inputs. If this
applies to your application, you may re-assign the location of these
pins in the UCF file.
<p>For applications where the user has implemented MSI capability in the
user configuration space, please note that this interface does not support
the assertion of SERR# by the user application. SERR# assertion is used
to signal MSI writes that have been abnormally terminated.
<h3>
3.4. <a NAME="Timing Simulation"></a>Timing Simulation</h3>
In all designs, timing violations may be reported during timing simulation.
This behavior is expected for two reasons. First, this interface
uses address stepping which can result in intermediate or unknown data
to be present on the bus during clock edges. Second, the timing
specifications used during place and route are very specific to eliminate
false timing paths; however, the simulation tool does not know which paths
are false and must report timing violations on all paths.
<h3>
3.5. <a NAME="Documentation"></a>Documentation</h3>
If you have downloaded the reduced fileset, Spartan-II only version of
this interface, please note that the examples in the Implementation Guide
use a device which is not available in this download. Please
note that you will need to follow the directions to target a device that
is available in this download; this includes changing the synthesis target
and modifying the Xilinx implementation scripts to select an available
part and package combination.
<h4>
<a href="#Release Notes">Back to Top</a></h4>
</td>
</tr>
</table>
<table COLS=1 WIDTH="596" >
<tr>
<td>
<h2>
4.0. <a NAME="Customer Support"></a>Customer Support</h2>
For registration, authorization codes, update information, warranty status,
shipping, product issues, and technical support, call Monday through Friday,
8 a.m. to 5 p.m. Pacific time.
<h3>
4.1. <a NAME="Registration"></a>Registration</h3>
You must be a registered customer to access the web based configuration
and download tool. If you have questions regarding your registration
status, or forget your password, you may contact Xilinx Customer Service
for assistance:
<br>
<table CELLSPACING=0 CELLPADDING=0 WIDTH="100%" >
<tr>
<td>United States and Canada</td>
<td>1-800-624-4782</td>
</tr>
<tr>
<td>International</td>
<td>Contact your local distributor</td>
</tr>
</table>
<h3>
4.2. <a NAME="Technical Support"></a>Technical Support</h3>
Technical support may be reached by the following means:
<br>
<table CELLSPACING=0 CELLPADDING=0 COLS=3 WIDTH="100%" >
<tr>
<td>North America</td>
<td>1-800-255-7778</td>
<td>hotline@xilinx.com</td>
</tr>
<tr>
<td>Japan</td>
<td>+81-03-5321-7750</td>
<td>jhotline@xilinx.com</td>
</tr>
<tr>
<td>France</td>
<td>+33-1-34-63-01-00</td>
<td>eurosupport@xilinx.com</td>
</tr>
<tr>
<td>Germany</td>
<td>+49-89-93088-130</td>
<td>eurosupport@xilinx.com</td>
</tr>
<tr>
<td>United Kingdom</td>
<td>+44-870-7350-610</td>
<td>eurosupport@xilinx.com</td>
</tr>
</table>
<h3>
4.3. <a NAME="Training"></a>Training</h3>
The Xilinx Training Administrator may be contacted at 1-408-879-5090.
International customers should contact a local sales representative or
distributor.
<h4>
<a href="#Release Notes">Back to Top</a></h4>
</td>
</tr>
</table>
</body>
</html>
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