leonardo.tcl

xilinx官方PCIcore 有详细说明文档

# LeonardoSpectrum Synthesis Script.  This script has been tested with
# LeonardoSpectrum v1991.1.  First, set the working directory to an
# appropriate location and modify the default synthesis environment.

cd <Install Path>/verilog/example/synthesis

set bubble_tristates FALSE
set novendor_constraint_file TRUE
set hdl_array_name_style %s<%d>

# Select the target device.  Change these commands to match your target.

load_library xcv
set part v300bg432
set process 6

# Read in the design from the bottom up.  These are the required files
# for the Ping example design.

read {
../../src/xpci/pci_lc_i.v
../../src/xpci/pcim_lc.v
../source/cfg_ping.v
../source/ping.v
../source/pcim_top.v
}

# Synthesize the entire design in one pass.  If you wish to synthesize
# the user application separately (often useful with larger designs),
# additional steps are required.  The example design synthesizes the
# user application and the "wrapper" files in one pass.  See the notes
# at the end of this file for more synthesis options.

present_design .work.pcim_top.INTERFACE

set_attribute AD* -name nopad -value FALSE -port 
set_attribute CBE* -name nopad -value FALSE -port 
set_attribute PAR -name nopad -value FALSE -port  
set_attribute PAR64 -name nopad -value FALSE -port 
set_attribute FRAME_N -name nopad -value FALSE -port 
set_attribute REQ64_N -name nopad -value FALSE -port  
set_attribute DEVSEL_N -name nopad -value FALSE -port 
set_attribute ACK64_N -name nopad -value FALSE -port 
set_attribute IRDY_N -name nopad -value FALSE -port 
set_attribute TRDY_N -name nopad -value FALSE -port
set_attribute STOP_N -name nopad -value FALSE -port  
set_attribute PERR_N -name nopad -value FALSE -port  
set_attribute SERR_N -name nopad -value FALSE -port  
set_attribute REQ_N -name nopad -value FALSE -port
set_attribute GNT_N -name nopad -value FALSE -port  
set_attribute IDSEL -name nopad -value FALSE -port 
set_attribute INTR_A -name nopad -value FALSE -port 
set_attribute RST_N -name nopad -value FALSE -port  
set_attribute PCLK -name nopad -value FALSE -port  

optimize -ta xcv -delay -effort quick -chip -hierarchy preserve

# Write out the database in the default format, and then auto_write
# the netlist in EDIF format for the Xilinx place and route tools.

write -format xdb pcim_top.xdb
auto_write -format edif pcim_top.edf

# This example synthesis script does not contain any timing constraints
# specific to the example design.  If you desire, you may add constraints
# to the design prior to the "optimize" step.

# For multi-pass synthesis, where the user application is compiled in
# separate optimization steps, each module must be optimized before the
# top level is optimized.  Furthermore, each submodule must be optimized
# with the "-macro" option to prevent the insertion of I/O buffers.
# Before the top level of the design (pcim_top) is optimized, a "dont_touch"
# must be applied to each of the pre-optimized modules.  Before writing
# the netlists, you must apply "undont_touch" to these modules so that the
# netlist is written properly.