ping_tb.v

来自「xilinx官方PCIcore 有详细说明文档」· Verilog 代码 · 共 229 行

/***********************************************************************
 
  File:   ping_tb.v
  Rev:    3.0.0

  This is an example top-level verilog testbench for the Ping user
  design.  It instantiates the Ping design, behavioral arbiter and
  target, and stimulus.  The design of individual components may be
  customized without affecting the top level.

  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.

***********************************************************************/
`timescale 1 ns / 1 ps


module ping_tb;


  // PCI Bus Signals

  wire   [63:0] AD;
  wire    [7:0] CBE;
  wire          PAR;
  wire          PAR64;
  tri1          FRAME_N;
  tri1          REQ64_N;
  tri1          TRDY_N;
  tri1          IRDY_N;
  tri1          STOP_N;
  tri1          DEVSEL_N;
  tri1          ACK64_N;
  wire          IDSEL;
  tri1          INTR_A;
  tri1          PERR_N;
  tri1          SERR_N;
  tri1          REQ_N;
  tri1          GNT_N;
  wire          RST_N;
  wire          CLK;

  wire          SINGLE;
  wire          PARK;
  wire          PING_DONE;
  wire          PING_REQUEST32;
  wire          PING_REQUEST64;


  // Instantiate master stimulus device

  stimulus STM (
                .AD( AD ),
                .CBE( CBE ),
                .PAR( PAR ),
                .PAR64( PAR64 ),
                .FRAME_N( FRAME_N ),
                .REQ64_N( REQ64_N ),
                .TRDY_N( TRDY_N ),
                .IRDY_N( IRDY_N ),
                .STOP_N( STOP_N ),
                .DEVSEL_N( DEVSEL_N ),
                .ACK64_N( ACK64_N ),
                .IDSEL( IDSEL ),
                .INTR_A( INTR_A ),
                .PERR_N( PERR_N ),
                .SERR_N( SERR_N ),
                .RST_N( RST_N ),
                .CLK( CLK ),
                .SINGLE( SINGLE ),
                .PARK( PARK ),
                .PING_DONE( PING_DONE ),
                .PING_REQUEST32( PING_REQUEST32 ),
                .PING_REQUEST64( PING_REQUEST64 )
                );


  // Instantiate arbiter

  dumb_arbiter ARB (
                .REQ_N( REQ_N ),
                .GNT_N( GNT_N ),
                .SINGLE( SINGLE ),
                .PARK( PARK ),
                .CLK( CLK )
                );


  // Instantiate FPGA PCI design

  pcim_top UUT (
                .AD( AD ),
                .CBE( CBE ),
                .PAR( PAR ),
                .PAR64( PAR64 ),
                .FRAME_N( FRAME_N ),
                .REQ64_N( REQ64_N ),
                .TRDY_N( TRDY_N ),
                .IRDY_N( IRDY_N ),
                .STOP_N( STOP_N ),
                .DEVSEL_N( DEVSEL_N ),
                .ACK64_N( ACK64_N ),
                .IDSEL( IDSEL ),
                .INTR_A( INTR_A ),
                .PERR_N( PERR_N ),
                .SERR_N( SERR_N ),
                .REQ_N( REQ_N ),
                .GNT_N( GNT_N ),
                .RST_N( RST_N ),
                .PCLK( CLK ),
                .PING_DONE( PING_DONE ),
                .PING_REQUEST32( PING_REQUEST32 ),
                .PING_REQUEST64( PING_REQUEST64 )
                );


  // Instantiate a 32-bit Target

  dumb_target32 TRG32 (
                .AD( AD[31:0] ),
                .CBE( CBE[3:0] ),
                .PAR( PAR ),
                .FRAME_N( FRAME_N ),
                .TRDY_N( TRDY_N ),
                .IRDY_N( IRDY_N ),
                .STOP_N( STOP_N ),
                .DEVSEL_N( DEVSEL_N ),
                .RST_N( RST_N ),
                .CLK( CLK )
                );


  // Instantiate a 64-bit Target

  dumb_target64 TRG64 (
                .AD( AD ),
                .CBE( CBE ),
                .PAR( PAR ),
                .PAR64( PAR64 ),
                .FRAME_N( FRAME_N ),
                .REQ64_N( REQ64_N ),
                .TRDY_N( TRDY_N ),
                .IRDY_N( IRDY_N ),
                .STOP_N( STOP_N ),
                .DEVSEL_N( DEVSEL_N ),
                .ACK64_N( ACK64_N ),
                .RST_N( RST_N ),
                .CLK( CLK )
                );


  // Start the simulation history manager.

  initial
  begin
    $shm_open("waves.shm");
    $shm_probe("AC");
  end


  // Instantiate a Bus Recorder

  busrecord REC (
                .AD( AD ),
                .CBE( CBE ),
                .PAR( PAR ),
                .PAR64( PAR64 ),
                .FRAME_N( FRAME_N ),
                .REQ64_N( REQ64_N ),
                .TRDY_N( TRDY_N ),
                .IRDY_N( IRDY_N ),
                .STOP_N( STOP_N ),
                .DEVSEL_N( DEVSEL_N ),
                .ACK64_N( ACK64_N ),
                .IDSEL( IDSEL ),
                .INTR_A( INTR_A ),
                .PERR_N( PERR_N ),
                .SERR_N( SERR_N ),
                .REQ_N( REQ_N ),
                .GNT_N( GNT_N ),
                .RST_N( RST_N ),
                .CLK( CLK )
                );


  // Extension pull ups

  pullup (PAR64);

  pullup (CBE[7]);
  pullup (CBE[6]);
  pullup (CBE[5]);
  pullup (CBE[4]);

  pullup (AD[63]);
  pullup (AD[62]);
  pullup (AD[61]);
  pullup (AD[60]);
  pullup (AD[59]);
  pullup (AD[58]);
  pullup (AD[57]);
  pullup (AD[56]);
  pullup (AD[55]);
  pullup (AD[54]);
  pullup (AD[53]);
  pullup (AD[52]);
  pullup (AD[51]);
  pullup (AD[50]);
  pullup (AD[49]);
  pullup (AD[48]);
  pullup (AD[47]);
  pullup (AD[46]);
  pullup (AD[45]);
  pullup (AD[44]);
  pullup (AD[43]);
  pullup (AD[42]);
  pullup (AD[41]);
  pullup (AD[40]);
  pullup (AD[39]);
  pullup (AD[38]);
  pullup (AD[37]);
  pullup (AD[36]);
  pullup (AD[35]);
  pullup (AD[34]);
  pullup (AD[33]);
  pullup (AD[32]);


endmodule