userapp.v

xilinx官方PCIcore 有详细说明文档

/***********************************************************************

  File:   userapp.v
  Rev:    3.0.0

  This is an example template for the user backend application.

  Copyright (c) 2003 Xilinx, Inc.  All rights reserved.

***********************************************************************/


module userapp (
                FRAMEQ_N,
                REQ64Q_N,
                TRDYQ_N,
                IRDYQ_N,
                STOPQ_N,
                DEVSELQ_N,
                ACK64Q_N,
                ADDR,
                ADIO,
                CFG_VLD,
                CFG_HIT,
                C_TERM,
                C_READY,
                ADDR_VLD,
                BASE_HIT,
                S_CYCLE64,
                S_TERM,
                S_READY,
                S_ABORT,
                S_WRDN,
                S_SRC_EN,
                S_DATA_VLD,
                S_CBE,
                PCI_CMD,
                REQUEST,
                REQUEST64,
                REQUESTHOLD,
                COMPLETE,
                M_WRDN,
                M_READY,
                M_SRC_EN,
                M_DATA_VLD,
                M_CBE,
                TIME_OUT,
                M_FAIL64,
                CFG_SELF,
                M_DATA,
                DR_BUS,
                I_IDLE,
                M_ADDR_N,
                IDLE,
                B_BUSY,
                S_DATA,
                BACKOFF,
                SLOT64,
                INTR_N,
                PERRQ_N,
                SERRQ_N,
                KEEPOUT,
                CSR,
                SUB_DATA,
                CFG,
                RST,
                CLK
                );
                // synthesis syn_edif_bit_format = "%u<%i>"
                // synthesis syn_edif_scalar_format = "%u"
                // synthesis syn_noclockbuf = 1 
                // synthesis syn_hier = "hard" 


  // Declare the port directions.

  input         FRAMEQ_N;
  input         REQ64Q_N;
  input         TRDYQ_N;
  input         IRDYQ_N;
  input         STOPQ_N;
  input         DEVSELQ_N;
  input         ACK64Q_N;
  input  [31:0] ADDR;
  inout  [63:0] ADIO;
  input         CFG_VLD;
  input         CFG_HIT;
  output        C_TERM;
  output        C_READY;
  input         ADDR_VLD;
  input   [7:0] BASE_HIT;
  input         S_CYCLE64;
  output        S_TERM;
  output        S_READY;
  output        S_ABORT;
  input         S_WRDN;
  input         S_SRC_EN;
  input         S_DATA_VLD;
  input   [7:0] S_CBE;
  input  [15:0] PCI_CMD;
  output        REQUEST;
  output        REQUEST64;
  output        REQUESTHOLD;
  output        COMPLETE;
  output        M_WRDN;
  output        M_READY;
  input         M_SRC_EN;
  input         M_DATA_VLD;
  output  [7:0] M_CBE;
  input         TIME_OUT;
  input         M_FAIL64;
  output        CFG_SELF;
  input         M_DATA;
  input         DR_BUS;
  input         I_IDLE;
  input         M_ADDR_N;
  input         IDLE;
  input         B_BUSY;
  input         S_DATA;
  input         BACKOFF;
  output        SLOT64;
  output        INTR_N;
  input         PERRQ_N;
  input         SERRQ_N;
  output        KEEPOUT;
  input  [39:0] CSR;
  output [31:0] SUB_DATA;
  input [255:0] CFG;
  input         RST;
  input         CLK;


  // Add user logic here


endmodule