max531.vhd

MAX531串行DA芯片的VHDL驱动

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity MAX531 is
port(
       clk_in: in std_logic;
       clk_out: buffer std_logic;
       --sa: in std_logic_vector(7 downto 0);
       da_data: in std_logic_vector(11 downto 0);
       sdi: out std_logic;
       cs_n: out std_logic;
       --reset: in std_logic;
       clr_n: out std_logic;
       -------------------------------------------------------------------------------------------
       count_out: out std_logic_vector(7 downto 0)
        
     );
end MAX531;

architecture DA1 of MAX531 is

  signal count: std_logic_vector(7 downto 0);
 


begin
 
  count_out <= count;

  CLR_n <= '1';
  clk_out <= clk_in;
  
  --process(clk_in)                                  --generate clk_out
  --  variable count1: std_logic_vector(5 downto 0);
  --begin
  --  if clk_in'event and clk_in = '1' then
  --  count1 := count1 + 1;
  --  end if;
  --  clk_out <= count1(3);
  --end process;
  
  process(clk_out)                                 --internal counter
  begin
    if clk_out'event and clk_out = '1' then
      if count /= 14 then
        count <= count +1;
      else
        count <= X"00";
      end if;
    end if;
  end process;



  process(clk_out)                                 --parallel data to serial data
  variable i: integer range 0 to 15;
  begin
    if clk_out'event and clk_out = '1' then
      if count = 0 then
        i := 12;
      end if;
      if  count /=13 then
        sdi <= da_data(i);
        i := i-1;
      end if;
    end if;
  end process;


  
  process(clk_out)
  begin
    if clk_out = '0' then
      
      if count > 0 and count < 13 then           --MAX531 CS singnal
        cs_n <= '0';
      else
        cs_n <= '1';
      end if;
    end if;
  end process;

end DA1;