_primary.vhd

来自「verilog 编写基于SRAM(CY7C1041)的代码」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity top_hc164_driver is
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        led             : in     vl_logic_vector(3 downto 0);
        seg_value       : in     vl_logic_vector(15 downto 0);
        dot             : in     vl_logic_vector(3 downto 0);
        hc_si           : out    vl_logic;
        hc_cp           : out    vl_logic
    );
end top_hc164_driver;