_primary.vhd

来自「verilog 编写基于SRAM(CY7C1041)的代码」· VHDL 代码 · 共 28 行

library verilog;
use verilog.vl_types.all;
entity sram_test1 is
    generic(
        idle            : integer := 0;
        wr_one          : integer := 1;
        wr_two          : integer := 2;
        wr_three        : integer := 3;
        rd_one          : integer := 4;
        rd_two          : integer := 5;
        rd_three        : integer := 6;
        rd_four         : integer := 7
    );
    port(
        rst_n           : in     vl_logic;
        clk             : in     vl_logic;
        sram_data       : inout  vl_logic_vector(15 downto 0);
        sram_addr       : out    vl_logic_vector(17 downto 0);
        sram_cs_n       : out    vl_logic;
        sram_we_n       : out    vl_logic;
        sram_ble_n      : out    vl_logic;
        sram_bhe_n      : out    vl_logic;
        sram_oe_n       : out    vl_logic;
        hc_si           : out    vl_logic;
        hc_cp           : out    vl_logic
    );
end sram_test1;