example_en_24bit_s.vh

来自「VHDL examples for counter design, use Qu」· VH 代码 · 共 9 行

/* Verilog Header Created from SCS Schematic example_en_24bit_s.sch 
   Aug 14, 2003 16:14 */


module example_en_24bit_s( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
 output [23:0] count_out;
input enable_in;