example_en_24bit_s.qdf

VHDL examples for counter design, use QuickLogic eclips

  end
  net enable
    gate I1 term Q end
    gate I6.I2 term E1 end
    gate I6.I2 term PS end
  end
  net enable_reg
    gate I6.I2 term QZ end
    gate I9.I10.I12 term F1 end
    gate I9.I10.I15 term F5 end
    gate I9.I11.I14 term F3 end
    gate I9.I11.I19 term F1 end
    gate I9.I9.I16 term A1 end
  end
  net count[23]
    gate I5.I6.I2 term PS end
    gate I9.I9.I12 term A1 end
    gate I9.I9.I18.I2 term QZ end
    gate I9.I9.I18.I2 term B1 end
    gate I9.I9.I18.I2 term C2 end
    gate I9.I9.I18.I1 term A5 end
  end
  net count[22]
    gate I5.I6.I2 term E1 end
    gate I9.I9.I12 term A3 end
    gate I9.I9.I18.I2 term F1 end
    gate I9.I9.I18.I1 term D1 end
    gate I9.I9.I18.I1 term E2 end
    gate I9.I9.I18.I1 term Q2Z end
  end
  net count[21]
    gate I5.I7.I2 term PS end
    gate I9.I9.I12 term A5 end
    gate I9.I9.I18.I1 term F1 end
    gate I9.I9.I18.I2 term F3 end
    gate I9.I9.I18.I1 term MS end
    gate I9.I9.I18.I1 term B2 end
    gate I9.I9.I18.I1 term C1 end
    gate I9.I9.I18.I1 term QZ end
  end
  net count[20]
    gate I5.I7.I2 term E1 end
    gate I9.I9.I12 term D1 end
    gate I9.I9.I18.I2 term A3 end
    gate I9.I9.I18.I2 term Q2Z end
    gate I9.I9.I18.I2 term D2 end
    gate I9.I9.I18.I2 term E1 end
    gate I9.I9.I18.I2 term F5 end
    gate I9.I9.I18.I1 term F3 end
    gate I9.I9.I18.I2 term NS end
  end
  net count[19]
    gate I5.I8.I2 term PS end
    gate I9.I9.I15 term A1 end
    gate I9.I9.I17.I2 term QZ end
    gate I9.I9.I17.I2 term B1 end
    gate I9.I9.I17.I2 term C2 end
    gate I9.I9.I17.I1 term A5 end
  end
  net count[18]
    gate I5.I8.I2 term E1 end
    gate I9.I9.I15 term A3 end
    gate I9.I9.I17.I2 term F1 end
    gate I9.I9.I17.I1 term D1 end
    gate I9.I9.I17.I1 term E2 end
    gate I9.I9.I17.I1 term Q2Z end
  end
  net count[17]
    gate I5.I9.I2 term PS end
    gate I9.I9.I15 term A5 end
    gate I9.I9.I17.I1 term F1 end
    gate I9.I9.I17.I2 term F3 end
    gate I9.I9.I17.I1 term MS end
    gate I9.I9.I17.I1 term B2 end
    gate I9.I9.I17.I1 term C1 end
    gate I9.I9.I17.I1 term QZ end
  end
  net count[16]
    gate I5.I9.I2 term E1 end
    gate I9.I9.I15 term D1 end
    gate I9.I9.I17.I2 term A3 end
    gate I9.I9.I17.I2 term Q2Z end
    gate I9.I9.I17.I2 term D2 end
    gate I9.I9.I17.I2 term E1 end
    gate I9.I9.I17.I2 term F5 end
    gate I9.I9.I17.I1 term F3 end
    gate I9.I9.I17.I2 term NS end
  end
  net count[15]
    gate I5.I2.I2 term PS end
    gate I9.I10.I12 term A1 end
    gate I9.I10.I17.I2 term QZ end
    gate I9.I10.I17.I2 term B1 end
    gate I9.I10.I17.I2 term C2 end
    gate I9.I10.I17.I1 term A5 end
  end
  net count[14]
    gate I5.I2.I2 term E1 end
    gate I9.I10.I12 term A3 end
    gate I9.I10.I17.I2 term F1 end
    gate I9.I10.I17.I1 term D1 end
    gate I9.I10.I17.I1 term E2 end
    gate I9.I10.I17.I1 term Q2Z end
  end
  net count[13]
    gate I5.I3.I2 term PS end
    gate I9.I10.I12 term A5 end
    gate I9.I10.I17.I1 term F1 end
    gate I9.I10.I17.I2 term F3 end
    gate I9.I10.I17.I1 term MS end
    gate I9.I10.I17.I1 term B2 end
    gate I9.I10.I17.I1 term C1 end
    gate I9.I10.I17.I1 term QZ end
  end
  net count[12]
    gate I5.I3.I2 term E1 end
    gate I9.I10.I12 term D1 end
    gate I9.I10.I17.I2 term A3 end
    gate I9.I10.I17.I2 term Q2Z end
    gate I9.I10.I17.I2 term D2 end
    gate I9.I10.I17.I2 term E1 end
    gate I9.I10.I17.I2 term F5 end
    gate I9.I10.I17.I1 term F3 end
    gate I9.I10.I17.I2 term NS end
  end
  net count[11]
    gate I5.I4.I2 term PS end
    gate I9.I10.I15 term A1 end
    gate I9.I10.I16.I2 term QZ end
    gate I9.I10.I16.I2 term B1 end
    gate I9.I10.I16.I2 term C2 end
    gate I9.I10.I16.I1 term A5 end
  end
  net count[10]
    gate I5.I4.I2 term E1 end
    gate I9.I10.I15 term A3 end
    gate I9.I10.I16.I2 term F1 end
    gate I9.I10.I16.I1 term D1 end
    gate I9.I10.I16.I1 term E2 end
    gate I9.I10.I16.I1 term Q2Z end
  end
  net count[9]
    gate I5.I5.I2 term PS end
    gate I9.I10.I15 term A5 end
    gate I9.I10.I16.I1 term F1 end
    gate I9.I10.I16.I2 term F3 end
    gate I9.I10.I16.I1 term MS end
    gate I9.I10.I16.I1 term B2 end
    gate I9.I10.I16.I1 term C1 end
    gate I9.I10.I16.I1 term QZ end
  end
  net count[8]
    gate I5.I5.I2 term E1 end
    gate I9.I10.I15 term D1 end
    gate I9.I10.I16.I2 term A3 end
    gate I9.I10.I16.I2 term Q2Z end
    gate I9.I10.I16.I2 term D2 end
    gate I9.I10.I16.I2 term E1 end
    gate I9.I10.I16.I2 term F5 end
    gate I9.I10.I16.I1 term F3 end
    gate I9.I10.I16.I2 term NS end
  end
  net count[7]
    gate I4.I3.I2 term PS end
    gate I9.I11.I19 term A1 end
    gate I9.I11.I21.I2 term QZ end
    gate I9.I11.I21.I2 term B1 end
    gate I9.I11.I21.I2 term C2 end
    gate I9.I11.I21.I1 term A5 end
  end
  net count[6]
    gate I4.I3.I2 term E1 end
    gate I9.I11.I19 term A3 end
    gate I9.I11.I21.I2 term F1 end
    gate I9.I11.I21.I1 term D1 end
    gate I9.I11.I21.I1 term E2 end
    gate I9.I11.I21.I1 term Q2Z end
  end
  net count[5]
    gate I4.I4.I2 term PS end
    gate I9.I11.I19 term A5 end
    gate I9.I11.I21.I1 term F1 end
    gate I9.I11.I21.I2 term F3 end
    gate I9.I11.I21.I1 term MS end
    gate I9.I11.I21.I1 term B2 end
    gate I9.I11.I21.I1 term C1 end
    gate I9.I11.I21.I1 term QZ end
  end
  net count[4]
    gate I4.I4.I2 term E1 end
    gate I9.I11.I19 term D1 end
    gate I9.I11.I21.I2 term A3 end
    gate I9.I11.I21.I2 term Q2Z end
    gate I9.I11.I21.I2 term D2 end
    gate I9.I11.I21.I2 term E1 end
    gate I9.I11.I21.I2 term F5 end
    gate I9.I11.I21.I1 term F3 end
    gate I9.I11.I21.I2 term NS end
  end
  net count[3]
    gate I4.I6.I2 term PS end
    gate I9.I11.I14 term A1 end
    gate I9.I11.I20.I2 term QZ end
    gate I9.I11.I20.I2 term B1 end
    gate I9.I11.I20.I2 term C2 end
    gate I9.I11.I20.I1 term A5 end
  end
  net count[2]
    gate I4.I6.I2 term E1 end
    gate I9.I11.I14 term A3 end
    gate I9.I11.I20.I2 term F1 end
    gate I9.I11.I20.I1 term D1 end
    gate I9.I11.I20.I1 term E2 end
    gate I9.I11.I20.I1 term Q2Z end
  end
  net count[1]
    gate I4.I5.I2 term PS end
    gate I9.I11.I14 term A5 end
    gate I9.I11.I20.I1 term F1 end
    gate I9.I11.I20.I2 term F3 end
    gate I9.I11.I20.I1 term MS end
    gate I9.I11.I20.I1 term B2 end
    gate I9.I11.I20.I1 term C1 end
    gate I9.I11.I20.I1 term QZ end
  end
  net count[0]
    gate I4.I5.I2 term E1 end
    gate I9.I11.I14 term E2 end
    gate I9.I11.I14 term D1 end
    gate I9.I11.I20.I2 term A3 end
    gate I9.I11.I20.I2 term Q2Z end
    gate I9.I11.I20.I2 term D2 end
    gate I9.I11.I20.I2 term E1 end
    gate I9.I11.I20.I2 term F5 end
    gate I9.I11.I20.I1 term F3 end
    gate I9.I11.I20.I2 term NS end
  end
  net count_reg[23]
    gate I5.I6.I2 term Q2Z end
    gate out_pad_25um[23] term A end
  end
  net count_reg[22]
    gate I5.I6.I2 term QZ end
    gate out_pad_25um[22] term A end
  end
  net count_reg[21]
    gate I5.I7.I2 term Q2Z end
    gate out_pad_25um[21] term A end
  end
  net count_reg[20]
    gate I5.I7.I2 term QZ end
    gate out_pad_25um[20] term A end
  end
  net count_reg[19]
    gate I5.I8.I2 term Q2Z end
    gate out_pad_25um[19] term A end
  end
  net count_reg[18]
    gate I5.I8.I2 term QZ end
    gate out_pad_25um[18] term A end
  end
  net count_reg[17]
    gate I5.I9.I2 term Q2Z end
    gate out_pad_25um[17] term A end
  end
  net count_reg[16]
    gate I5.I9.I2 term QZ end
    gate out_pad_25um[16] term A end
  end
  net count_reg[15]
    gate I5.I2.I2 term Q2Z end
    gate out_pad_25um[15] term A end
  end
  net count_reg[14]
    gate I5.I2.I2 term QZ end
    gate out_pad_25um[14] term A end
  end
  net count_reg[13]
    gate I5.I3.I2 term Q2Z end
    gate out_pad_25um[13] term A end
  end
  net count_reg[12]
    gate I5.I3.I2 term QZ end
    gate out_pad_25um[12] term A end
  end
  net count_reg[11]
    gate I5.I4.I2 term Q2Z end
    gate out_pad_25um[11] term A end
  end
  net count_reg[10]
    gate I5.I4.I2 term QZ end
    gate out_pad_25um[10] term A end
  end
  net count_reg[9]
    gate I5.I5.I2 term Q2Z end
    gate out_pad_25um[9] term A end
  end
  net count_reg[8]
    gate I5.I5.I2 term QZ end
    gate out_pad_25um[8] term A end
  end
  net count_reg[7]
    gate I4.I3.I2 term Q2Z end
    gate out_pad_25um[7] term A end
  end
  net count_reg[6]
    gate I4.I3.I2 term QZ end
    gate out_pad_25um[6] term A end
  end
  net count_reg[5]
    gate I4.I4.I2 term Q2Z end
    gate out_pad_25um[5] term A end
  end
  net count_reg[4]
    gate I4.I4.I2 term QZ end
    gate out_pad_25um[4] term A end
  end
  net count_reg[3]
    gate I4.I6.I2 term Q2Z end
    gate out_pad_25um[3] term A end
  end
  net count_reg[2]
    gate I4.I6.I2 term QZ end
    gate out_pad_25um[2] term A end
  end
  net count_reg[1]
    gate I4.I5.I2 term Q2Z end
    gate out_pad_25um[1] term A end
  end
  net count_reg[0]
    gate I4.I5.I2 term QZ end
    gate out_pad_25um[0] term A end
  end
  net count_out[23] direction output
    gate out_pad_25um[23] term P end
  end
  net count_out[22] direction output
    gate out_pad_25um[22] term P end
  end
  net count_out[21] direction output
    gate out_pad_25um[21] term P end
  end
  net count_out[20] direction output
    gate out_pad_25um[20] term P end
  end
  net count_out[19] direction output
    gate out_pad_25um[19] term P end
  end
  net count_out[18] direction output
    gate out_pad_25um[18] term P end
  end
  net count_out[17] direction output
    gate out_pad_25um[17] term P end
  end
  net count_out[16] direction output
    gate out_pad_25um[16] term P end
  end
  net count_out[15] direction output
    gate out_pad_25um[15] term P end
  end
  net count_out[14] direction output
    gate out_pad_25um[14] term P end
  end
  net count_out[13] direction output
    gate out_pad_25um[13] term P end
  end
  net count_out[12] direction output
    gate out_pad_25um[12] term P end
  end
  net count_out[11] direction output
    gate out_pad_25um[11] term P end
  end
  net count_out[10] direction output
    gate out_pad_25um[10] term P end
  end
  net count_out[9] direction output
    gate out_pad_25um[9] term P end
  end
  net count_out[8] direction output
    gate out_pad_25um[8] term P end
  end
  net count_out[7] direction output
    gate out_pad_25um[7] term P end
  end
  net count_out[6] direction output
    gate out_pad_25um[6] term P end
  end
  net count_out[5] direction output
    gate out_pad_25um[5] term P end
  end
  net count_out[4] direction output
    gate out_pad_25um[4] term P end
  end
  net count_out[3] direction output
    gate out_pad_25um[3] term P end
  end
  net count_out[2] direction output
    gate out_pad_25um[2] term P end
  end
  net count_out[1] direction output
    gate out_pad_25um[1] term P end
  end
  net count_out[0] direction output
    gate out_pad_25um[0] term P end
  end
  net clk_in direction input
    gate I3 term P end
  end
  net clear_in direction input
    gate I2 term P end
  end
  net enable_in direction input
    gate I1 term P end
  end
  net .I4.I3.I2-AZ direction output
    gate I4.I3.I2 term AZ end
  end
  net .I4.I3.I2-OZ direction output
    gate I4.I3.I2 term OZ end
  end
  net .I4.I3.I2-NZ direction output
    gate I4.I3.I2 term NZ end
  end
  net .I4.I3.I2-FZ direction output
    gate I4.I3.I2 term FZ end
  end
  net .I4.I4.I2-AZ direction output
    gate I4.I4.I2 term AZ end
  end
  net .I4.I4.I2-OZ direction output
    gate I4.I4.I2 term OZ end
  end
  net .I4.I4.I2-NZ direction output
    gate I4.I4.I2 term NZ end
  end
  net .I4.I4.I2-FZ direction output
    gate I4.I4.I2 term FZ end
  end
  net .I4.I5.I2-AZ direction output
    gate I4.I5.I2 term AZ end
  end
  net .I4.I5.I2-OZ direction output
    gate I4.I5.I2 term OZ end
  end
  net .I4.I5.I2-NZ direction output
    gate I4.I5.I2 term NZ end
  end
  net .I4.I5.I2-FZ direction output
    gate I4.I5.I2 term FZ end
  end
  net .I4.I6.I2-AZ direction output
    gate I4.I6.I2 term AZ end
  end
  net .I4.I6.I2-OZ direction output
    gate I4.I6.I2 term OZ end
  end