example_en_8bit_s.chp

VHDL examples for counter design, use QuickLogic eclips

      port NP net GND
      port OP net GND
      port PS net count[7]
    end
  end
  cell PLLIN2
    gate I6
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clear
      port IP net clear_in
    end
  end
  cell PLLIN0
    gate I5
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clk
      port IP net clk_in
    end
  end
  cell IO279
    gate I3.I2
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[1]
      port OQI net count_reg[1]
    end
  end
  cell IO280
    gate I3.I1
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[0]
      port OQI net count_reg[0]
    end
  end
  cell IO285
    gate I4
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net enable
      port OQI net VCC
      port IE net GND
      port IP net enable_in
    end
  end
  cell IO287
    gate I9.I17
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net .I9-f_enable_2
      port OQI net .I9-enable_2_r
    end
  end
  cell IO288
    gate I3.I6
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[5]
      port OQI net count_reg[5]
    end
  end
  cell IO289
    gate I9.I18
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net .I9-f_enable_1
      port OQI net .I9-enable_1_a
    end
  end
  cell IO290
    gate I3.I5
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[4]
      port OQI net count_reg[4]
    end
  end
  cell IO293
    gate I3.I3
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[2]
      port OQI net count_reg[2]
    end
  end
  cell IO297
    gate I3.I4
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[3]
      port OQI net count_reg[3]
    end
  end
  cell IO298
    gate I3.I8
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[7]
      port OQI net count_reg[7]
    end
  end
  cell IO299
    gate I3.I7
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[6]
      port OQI net count_reg[6]
    end
  end
end
route
  net clk
  wire B6.DCLK port B6.DCLK end
  wire B5.DCLK port B5.DCLK end
  wire A5.DCLK port A5.DCLK end
  wire A4.DCLK port A4.DCLK end
  wire B3.DCLK port B3.DCLK end
  wire B4.DCLK port B4.DCLK end
  wire B2.DCLK port B2.DCLK end
  wire A6.DCLK port A6.DCLK end
  wire B1.DCLK port B1.DCLK end
  wire A3.DCLK port A3.DCLK end
  wire A7.DCLK port A7.DCLK end
  wire V. 1.42. 0 end
  wire V. 2. 0. 0 end
  net clear
  wire B6.QR port B6.QR wire V. 2.14. 0 branch
    wire B4.QR port B4.QR end
    wire B3.QR port B3.QR end
    wire B5.QR port B5.QR end
  end
  wire A5.QR port A5.QR wire V. 1.28. 0 wire A4.QR port A4.QR end
  net enable
  wire IO285.IZ port IO285.IZ wire H. 9.30. 0 wire V. 2.24. 8 wire B2.PS port B2.PS end
  net enable_reg
  wire B3.F1 port B3.F1 wire V. 2.42. 7 branch
    wire B4.NS port B4.NS end
    wire B4.F3 port B4.F3 end
    wire B2.Q2Z port B2.Q2Z end
  end
  net count[7]
  wire A5.C2 port A5.C2 wire V. 1. 5.11 branch
    wire A7.PS port A7.PS end
    wire A4.A5 port A4.A5 end
    wire H.13.28. 0 wire V. 2. 6.12 wire V. 2. 6.10 wire B3.A1 port B3.A1 end
    wire A5.B1 port A5.B1 end
    wire A5.QZ port A5.QZ end
  end
  net count[6]
  wire A5.F1 port A5.F1 wire V. 1. 9.11 branch
    wire A7.E1 port A7.E1 end
    wire A4.E2 port A4.E2 end
    wire H.11.12. 0 wire V. 2. 8.10 wire B3.A3 port B3.A3 end
    wire A4.D1 port A4.D1 end
    wire A4.Q2Z port A4.Q2Z end
  end
  net count[5]
  wire A5.F3 port A5.F3 wire V. 1.39.13 wire V. 1.39.11 branch
    wire A4.F1 port A4.F1 end
    wire A4.MS port A4.MS end
    wire V. 1.39. 9 wire A3.PS port A3.PS end
    wire H.11.14. 0 wire V. 2.10.10 wire B3.A5 port B3.A5 end
    wire A4.C1 port A4.C1 end
    wire A4.B2 port A4.B2 end
    wire A4.QZ port A4.QZ end
  end
  net count[4]
  wire A5.NS port A5.NS wire V. 1. 4. 7 branch
    wire A4.F3 port A4.F3 end
    wire A3.E1 port A3.E1 end
    wire H.11.28. 0 wire V. 2.22.10 wire B3.MS port B3.MS end
    wire A5.F5 port A5.F5 end
    wire A5.E1 port A5.E1 end
    wire A5.D2 port A5.D2 end
    wire A5.A3 port A5.A3 end
    wire A5.Q2Z port A5.Q2Z end
  end
  net count[3]
  wire B6.C2 port B6.C2 wire V. 2.23.15 branch
    wire V. 2.23.13 branch
      wire B5.A5 port B5.A5 end
      wire V. 2.23.11 wire B4.A1 port B4.A1 end
    end
    wire H.15.28. 0 wire V. 1.37.15 wire A6.PS port A6.PS end
    wire B6.B1 port B6.B1 end
    wire B6.QZ port B6.QZ end
  end
  net count[2]
  wire B6.F1 port B6.F1 wire V. 2.24.16 wire V. 2.24.14 branch
    wire B5.E2 port B5.E2 end
    wire V. 2.24.12 wire B4.A3 port B4.A3 end
    wire H.15.30. 0 wire V. 1.39.15 wire A6.E1 port A6.E1 end
    wire B5.D1 port B5.D1 end
    wire B5.Q2Z port B5.Q2Z end
  end
  net count[1]
  wire B6.F3 port B6.F3 wire V. 2.26.16 wire V. 2.26.14 branch
    wire B5.F1 port B5.F1 end
    wire B5.MS port B5.MS end
    wire V. 2.26.12 branch
      wire B4.A5 port B4.A5 end
      wire V. 2.26.10 wire V. 2.26. 8 wire V. 2.26. 6 wire B1.PS port B1.PS end
    end
    wire B5.C1 port B5.C1 end
    wire B5.B2 port B5.B2 end
    wire B5.QZ port B5.QZ end
  end
  net count[0]
  wire B6.NS port B6.NS wire V. 2.28.16 branch
    wire V. 2.28.14 branch
      wire B5.F3 port B5.F3 end
      wire V. 2.28.12 branch
        wire B4.E2 port B4.E2 end
        wire V. 2.28.10 wire V. 2.28. 8 wire V. 2.28. 6 wire B1.E1 port B1.E1 end
        wire B4.D1 port B4.D1 end
      end
    end
    wire B6.F5 port B6.F5 end
    wire B6.E1 port B6.E1 end
    wire B6.D2 port B6.D2 end
    wire B6.A3 port B6.A3 end
    wire B6.Q2Z port B6.Q2Z end
  end
  net count_reg[7]
  wire IO298.OQI port IO298.OQI wire H.19.27. 0 wire V. 1.36.18 wire A7.Q2Z port A7.Q2Z end
  net count_reg[6]
  wire IO299.OQI port IO299.OQI wire H.19.29. 0 wire V. 1.38.18 wire A7.QZ port A7.QZ end
  net count_reg[5]
  wire IO288.OQI port IO288.OQI wire H.11.29. 0 wire V. 1.34.10 wire A3.Q2Z port A3.Q2Z end
  net count_reg[4]
  wire IO290.OQI port IO290.OQI wire H.13.29. 0 wire V. 1.36.12 wire V. 1.36.10 wire A3.QZ port A3.QZ end
  net count_reg[3]
  wire IO297.OQI port IO297.OQI wire H.17.27. 0 wire V. 1.36.16 wire A6.Q2Z port A6.Q2Z end
  net count_reg[2]
  wire IO293.OQI port IO293.OQI wire H.17.29. 0 wire V. 1.38.16 wire A6.QZ port A6.QZ end
  net count_reg[1]
  wire IO279.OQI port IO279.OQI wire V. 2.25. 0 wire V. 2.25. 3 wire B1.Q2Z port B1.Q2Z end
  net count_reg[0]
  wire IO280.OQI port IO280.OQI wire V. 2.27. 0 wire V. 2.27. 3 wire B1.QZ port B1.QZ end
  net .I9-enable_2_r
  wire B3.QZ port B3.QZ wire V. 2.24.10 wire H.11.23. 0 wire IO287.OQI port IO287.OQI end
  net .I9-enable_buf_a
  wire B6.MP port B6.MP wire V. 2.40. 9 branch
    wire B5.NP port B5.NP end
    wire B6.E2 port B6.E2 end
    wire B6.D1 port B6.D1 end
    wire B6.A1 port B6.A1 end
    wire B3.FZ port B3.FZ end
  end
  net .I9-fo_enable_r
  wire B4.F1 port B4.F1 wire V. 2.25.11 wire B4.QZ port B4.QZ end
  net .I9-enable_1_a
  wire A3.A1 port A3.A1 wire V. 1.38.10 wire H.11.30. 0 wire V. 2.27.11 branch
    wire V. 2.27.13 wire H.13.30. 0 wire IO289.OQI port IO289.OQI end
    wire B4.FZ port B4.FZ end
  end
  net .I9.I20-ED_a
  wire A5.AZ port A5.AZ wire V. 1.35.13 wire V. 1.35.11 branch
    wire A4.C2 port A4.C2 end
    wire A4.B1 port A4.B1 end
    wire A4.A3 port A4.A3 end
  end
  net .I9.I20-BCD_a
  wire A5.FZ port A5.FZ wire V. 1.37.13 wire V. 1.37.11 wire A4.A1 port A4.A1 end
  net .I9.I21-ED_a
  wire B6.AZ port B6.AZ wire V. 2.21.15 wire V. 2.21.13 branch
    wire B5.C2 port B5.C2 end
    wire B5.B1 port B5.B1 end
    wire B5.A3 port B5.A3 end
  end
  net .I9.I21-BCD_a
  wire B6.FZ port B6.FZ wire V. 2.25.15 wire V. 2.25.13 wire B5.A1 port B5.A1 end
  net .I9-enable_1_a_LRBUF0
  wire A4.NP port A4.NP wire V. 1. 8. 7 branch
    wire A5.MP port A5.MP end
    wire A5.E2 port A5.E2 end
    wire A5.D1 port A5.D1 end
    wire A5.A1 port A5.A1 end
    wire A3.AZ port A3.AZ end
  end
end
delay
    port B6.DCLK  delay rise 0.147 fall 0.194 slew rise 0.185 fall 0.248 end
    port B5.DCLK  delay rise 0.169 fall 0.217 slew rise 0.279 fall 0.338 end
    port A5.DCLK  delay rise 0.171 fall 0.217 slew rise 0.204 fall 0.264 end
    port A4.DCLK  delay rise 0.190 fall 0.237 slew rise 0.308 fall 0.292 end
    port B3.DCLK  delay rise 0.213 fall 0.260 slew rise 0.312 fall 0.352 end
    port B4.DCLK  delay rise 0.192 fall 0.239 slew rise 0.271 fall 0.298 end
    port B2.DCLK  delay rise 0.232 fall 0.279 slew rise 0.344 fall 0.293 end
    port A6.DCLK  delay rise 0.151 fall 0.197 slew rise 0.213 fall 0.234 end
    port B1.DCLK  delay rise 0.249 fall 0.295 slew rise 0.308 fall 0.377 end
    port A3.DCLK  delay rise 0.209 fall 0.255 slew rise 0.259 fall 0.312 end
    port A7.DCLK  delay rise 0.133 fall 0.176 slew rise 0.078 fall 0.181 end
    port B6.QR  delay rise 0.178 fall 0.206 slew rise 0.309 fall 0.286 end
    port B5.QR  delay rise 0.208 fall 0.234 slew rise 0.329 fall 0.320 end
    port A5.QR  delay rise 0.186 fall 0.213 slew rise 0.279 fall 0.296 end
    port A4.QR  delay rise 0.208 fall 0.234 slew rise 0.331 fall 0.341 end
    port B3.QR  delay rise 0.257 fall 0.282 slew rise 0.389 fall 0.370 end
    port B4.QR  delay rise 0.234 fall 0.260 slew rise 0.334 fall 0.358 end
    port B2.PS  delay rise 0.182 fall 0.164 slew rise 0.251 fall 0.212 end
    port B3.F1  delay rise 0.210 fall 0.187 slew rise 0.320 fall 0.277 end
    port B4.NS  delay rise 0.218 fall 0.195 slew rise 0.309 fall 0.273 end
    port B4.F3  delay rise 0.218 fall 0.195 slew rise 0.309 fall 0.273 end
    port A5.C2  delay rise 0.347 fall 0.302 slew rise 0.637 fall 0.531 end
    port A5.B1  delay rise 0.348 fall 0.303 slew rise 0.636 fall 0.529 end
    port A4.A5  delay rise 0.362 fall 0.317 slew rise 0.624 fall 0.382 end
    port B3.A1  delay rise 0.455 fall 0.407 slew rise 0.675 fall 0.468 end
    port A7.PS  delay rise 0.357 fall 0.311 slew rise 0.629 fall 0.362 end
    port A5.F1  delay rise 0.339 fall 0.299 slew rise 0.550 fall 0.440 end
    port A4.E2  delay rise 0.330 fall 0.290 slew rise 0.576 fall 0.421 end
    port A4.D1  delay rise 0.331 fall 0.290 slew rise 0.574 fall 0.423 end
    port B3.A3  delay rise 0.390 fall 0.350 slew rise 0.612 fall 0.554 end
    port A7.E1  delay rise 0.350 fall 0.309 slew rise 0.499 fall 0.462 end
    port A5.F3  delay rise 0.409 fall 0.359 slew rise 0.587 fall 0.616 end
    port A4.MS  delay rise 0.388 fall 0.338 slew rise 0.668 fall 0.586 end
    port A4.F1  delay rise 0.388 fall 0.338 slew rise 0.668 fall 0.586 end
    port A4.C1  delay rise 0.389 fall 0.339 slew rise 0.666 fall 0.586 end
    port A4.B2  delay rise 0.388 fall 0.338 slew rise 0.668 fall 0.586 end
    port B3.A5  delay rise 0.453 fall 0.402 slew rise 0.716 fall 0.575 end
    port A3.PS  delay rise 0.419 fall 0.368 slew rise 0.602 fall 0.608 end
    port A5.NS  delay rise 0.402 fall 0.351 slew rise 0.736 fall 0.534 end
    port A5.F5  delay rise 0.402 fall 0.351 slew rise 0.736 fall 0.534 end
    port A5.E1  delay rise 0.402 fall 0.351 slew rise 0.734 fall 0.536 end
    port A5.D2  delay rise 0.402 fall 0.351 slew rise 0.736 fall 0.534 end
    port A5.A3  delay rise 0.402 fall 0.351 slew rise 0.736 fall 0.534 end
    port A4.F3  delay rise 0.426 fall 0.375 slew rise 0.634 fall 0.590 end
    port B3.MS  delay rise 0.489 fall 0.437 slew rise 0.771 fall 0.632 end
    port A3.E1  delay rise 0.442 fall 0.390 slew rise 0.650 fall 0.840 end
    port B6.C2  delay rise 0.326 fall 0.281 slew rise 0.623 fall 0.470 end
    port B6.B1  delay rise 0.327 fall 0.282 slew rise 0.622 fall 0.471 end
    port B5.A5  delay rise 0.381 fall 0.335 slew rise 0.569 fall 0.581 end
    port B4.A1  delay rise 0.403 fall 0.356 slew rise 0.661 fall 0.521 end
    port A6.PS  delay rise 0.396 fall 0.351 slew rise 0.581 fall 0.534 end
    port B6.F1  delay rise 0.367 fall 0.321 slew rise 0.538 fall 0.497 end
    port B5.E2  delay rise 0.336 fall 0.291 slew rise 0.585 fall 0.421 end
    port B5.D1  delay rise 0.336 fall 0.292 slew rise 0.583 fall 0.423 end
    port B4.A3  delay rise 0.357 fall 0.312 slew rise 0.523 fall 0.471 end
    port A6.E1  delay rise 0.405 fall 0.359 slew rise 0.616 fall 0.553 end
    port B6.F3  delay rise 0.389 fall 0.336 slew rise 0.684 fall 0.540 end
    port B5.MS  delay rise 0.367 fall 0.313 slew rise 0.711 fall 0.496 end
    port B5.F1  delay rise 0.367 fall 0.313 slew rise 0.711 fall 0.496 end
    port B5.C1  delay rise 0.368 fall 0.314 slew rise 0.710 fall 0.498 end
    port B5.B2  delay rise 0.367 fall 0.313 slew rise 0.711 fall 0.496 end
    port B4.A5  delay rise 0.440 fall 0.383 slew rise 0.687 fall 0.729 end
    port B1.PS  delay rise 0.541 fall 0.482 slew rise 0.663 fall 0.763 end
    port B6.NS  delay rise 0.380 fall 0.322 slew rise 0.824 fall 0.701 end
    port B6.F5  delay rise 0.380 fall 0.322 slew rise 0.824 fall 0.701 end
    port B6.E1  delay rise 0.381 fall 0.322 slew rise 0.824 fall 0.699 end
    port B6.D2  delay rise 0.380 fall 0.322 slew rise 0.824 fall 0.701 end
    port B6.A3  delay rise 0.380 fall 0.322 slew rise 0.824 fall 0.701 end
    port B5.F3  delay rise 0.496 fall 0.429 slew rise 1.108 fall 0.803 end
    port B4.E2  delay rise 0.581 fall 0.510 slew rise 0.747 fall 0.726 end
    port B4.D1  delay rise 0.582 fall 0.511 slew rise 0.748 fall 0.729 end
    port B1.E1  delay rise 0.686 fall 0.612 slew rise 1.095 fall 0.753 end
    port IO298.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO299.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO288.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO290.OQI  delay rise 0.223 fall 0.201 slew rise 0.297 fall 0.276 end
    port IO297.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO293.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO279.OQI  delay rise 0.357 fall 0.326 slew rise 0.502 fall 0.393 end
    port IO280.OQI  delay rise 0.357 fall 0.326 slew rise 0.502 fall 0.393 end
    port IO287.OQI  delay rise 0.221 fall 0.196 slew rise 0.330 fall 0.260 end
    port B6.MP  delay rise 0.288 fall 0.257 slew rise 0.480 fall 0.429 end
    port B6.E2  delay rise 0.288 fall 0.257 slew rise 0.480 fall 0.429 end
    port B6.D1  delay rise 0.289 fall 0.258 slew rise 0.479 fall 0.428 end
    port B6.A1  delay rise 0.288 fall 0.257 slew rise 0.480 fall 0.429 end
    port B5.NP  delay rise 0.276 fall 0.244 slew rise 0.410 fall 0.365 end
    port B4.F1  delay rise 0.105 fall 0.094 slew rise 0.123 fall 0.117 end
    port A3.A1  delay rise 0.333 fall 0.296 slew rise 0.542 fall 0.448 end
    port IO289.OQI  delay rise 0.338 fall 0.302 slew rise 0.536 fall 0.434 end
    port A4.C2  delay rise 0.216 fall 0.191 slew rise 0.335 fall 0.254 end
    port A4.B1  delay rise 0.217 fall 0.192 slew rise 0.334 fall 0.255 end
    port A4.A3  delay rise 0.216 fall 0.191 slew rise 0.335 fall 0.254 end
    port A4.A1  delay rise 0.150 fall 0.134 slew rise 0.188 fall 0.172 end
    port B5.C2  delay rise 0.216 fall 0.191 slew rise 0.335 fall 0.254 end
    port B5.B1  delay rise 0.217 fall 0.192 slew rise 0.334 fall 0.255 end
    port B5.A3  delay rise 0.216 fall 0.191 slew rise 0.335 fall 0.254 end
    port B5.A1  delay rise 0.150 fall 0.134 slew rise 0.188 fall 0.172 end
    port A4.NP  delay rise 0.264 fall 0.234 slew rise 0.372 fall 0.317 end
    port A5.A1  delay rise 0.277 fall 0.246 slew rise 0.384 fall 0.356 end
    port A5.D1  delay rise 0.278 fall 0.247 slew rise 0.385 fall 0.480 end
    port A5.E2  delay rise 0.277 fall 0.246 slew rise 0.384 fall 0.356 end
    port A5.MP  delay rise 0.277 fall 0.246 slew rise 0.384 fall 0.356 end
end