example_en_8bit_s.chp

VHDL examples for counter design, use QuickLogic eclips

    gate I9.I20.I2 term A5 end
    gate I9.I20.I2 term C1 end
    gate I9.I21.I1 term E1 end
    gate I9.I21.I1 term F5 end
    gate I9.I21.I2 term A5 end
    gate I9.I21.I2 term C1 end
  end
end
place up
  cell B1
    gate I1.I5.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[1]
      port QZ net count_reg[0]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[0]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[1]
    end
  end
  cell B2
    gate I2.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term QZ port Q2Z end
    end
    block fragments S;
      port Q2Z net enable_reg
      port DCLK net clk
      port CLKSEL net GND
      port PS net enable
    end
  end
  cell A3
    gate I1.I4.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block blockbuffer fragments A;
      port AZ net .I9-enable_1_a_LRBUF0
      port A1 net .I9-enable_1_a
    end
    block fragments ONQS;
      port Q2Z net count_reg[5]
      port QZ net count_reg[4]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[4]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[5]
    end
  end
  cell B3
    gate I9.I19
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term C1 port C1 end
      term D1 port D1 end
      term E1 port E1 end
      term F1 port F1 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OS port OS end
      term QR port QR end
      term FZ port FZ end
      term QZ port QZ end
    end
    block fragments AFONQ;
      port FZ net .I9-enable_buf_a
      port QZ net .I9-enable_2_r
      port DCLK net clk
      port CLKSEL net GND
      port A1 net count[7]
      port A3 net count[6]
      port A5 net count[5]
      port C1 net GND
      port D1 net GND
      port E1 net GND
      port F1 net enable_reg
      port MP net GND
      port MS net count[4]
      port NP net GND
      port NS net GND
      port OS net GND
      port QR net clear
    end
  end
  cell A4
    gate I9.I20.I1
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term B1 port B1 end
      term B2 port B2 end
      term C1 port C1 end
      term C2 port C2 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port Q2Z net count[6]
      port QZ net count[5]
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I9.I20-BCD_a
      port A3 net .I9.I20-ED_a
      port A5 net count[7]
      port B1 net .I9.I20-ED_a
      port B2 net count[5]
      port C1 net count[5]
      port C2 net .I9.I20-ED_a
      port D1 net count[6]
      port E2 net count[6]
      port F1 net count[5]
      port F3 net count[4]
      port MP net GND
      port MS net count[5]
      port NP net .I9-enable_1_a_LRBUF0
      port NS net GND
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell B4
    gate I9.I14
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OS port OS end
      term QR port QR end
      term FZ port FZ end
      term QZ port QZ end
    end
    block fragments AFONQ;
      port FZ net .I9-enable_1_a
      port QZ net .I9-fo_enable_r
      port DCLK net clk
      port CLKSEL net GND
      port A1 net count[3]
      port A3 net count[2]
      port A5 net count[1]
      port B1 net GND
      port C1 net GND
      port D1 net count[0]
      port E2 net count[0]
      port F1 net .I9-fo_enable_r
      port F3 net enable_reg
      port MP net GND
      port MS net GND
      port NP net GND
      port NS net enable_reg
      port OS net GND
      port QR net clear
    end
  end
  cell A5
    gate I9.I20.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term B1 port B1 end
      term C2 port C2 end
      term D1 port D1 end
      term D2 port D2 end
      term E1 port E1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term F5 port F5 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term AZ port AZ end
      term FZ port FZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I9.I20-ED_a
      port FZ net .I9.I20-BCD_a
      port Q2Z net count[4]
      port QZ net count[7]
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I9-enable_1_a_LRBUF0
      port A3 net count[4]
      port B1 net count[7]
      port C2 net count[7]
      port D1 net .I9-enable_1_a_LRBUF0
      port D2 net count[4]
      port E1 net count[4]
      port E2 net .I9-enable_1_a_LRBUF0
      port F1 net count[6]
      port F3 net count[5]
      port F5 net count[4]
      port MP net .I9-enable_1_a_LRBUF0
      port MS net GND
      port NP net GND
      port NS net count[4]
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell B5
    gate I9.I21.I1
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term B1 port B1 end
      term B2 port B2 end
      term C1 port C1 end
      term C2 port C2 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port Q2Z net count[2]
      port QZ net count[1]
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I9.I21-BCD_a
      port A3 net .I9.I21-ED_a
      port A5 net count[3]
      port B1 net .I9.I21-ED_a
      port B2 net count[1]
      port C1 net count[1]
      port C2 net .I9.I21-ED_a
      port D1 net count[2]
      port E2 net count[2]
      port F1 net count[1]
      port F3 net count[0]
      port MP net GND
      port MS net count[1]
      port NP net .I9-enable_buf_a
      port NS net GND
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell A6
    gate I1.I6.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[3]
      port QZ net count_reg[2]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[2]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[3]
    end
  end
  cell B6
    gate I9.I21.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term B1 port B1 end
      term C2 port C2 end
      term D1 port D1 end
      term D2 port D2 end
      term E1 port E1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term F5 port F5 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term AZ port AZ end
      term FZ port FZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I9.I21-ED_a
      port FZ net .I9.I21-BCD_a
      port Q2Z net count[0]
      port QZ net count[3]
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I9-enable_buf_a
      port A3 net count[0]
      port B1 net count[3]
      port C2 net count[3]
      port D1 net .I9-enable_buf_a
      port D2 net count[0]
      port E1 net count[0]
      port E2 net .I9-enable_buf_a
      port F1 net count[2]
      port F3 net count[1]
      port F5 net count[0]
      port MP net .I9-enable_buf_a
      port MS net GND
      port NP net GND
      port NS net count[0]
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell A7
    gate I1.I3.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[7]
      port QZ net count_reg[6]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[6]
      port MP net GND