example_en_4bit.vh

来自「VHDL examples for counter design, use Qu」· VH 代码 · 共 9 行

/* Verilog Header Created from SCS Schematic example_en_4bit.sch 
   Aug 13, 2003 12:30 */


module example_en_4bit( clear_in , clk_in, enable_in, count_out );
input clear_in, clk_in;
 output [3:0] count_out;
input enable_in;