example_en_4bit_new.qdf

VHDL examples for counter design, use QuickLogic eclips

# Created by ECS2SPDE version 9.5 Release Build2
# Wed Aug 13 12:30:46 2003

QDIF 3
file ql8325
package PS484
tools
  design 9500
end
library EXAMPLE_EN_4BIT
  gates 5
  terms 56
  ports 82
  gate INPAD_25UM cell BIDIR
    term vcc port OSEL port OQI port ESEL port EQE end
    term gnd port IQC port IE port IQE port IQR end
    term P port IP end
    term Q port IZ end
  end
  gate CKPAD_25UM cell CLOCK
    term P port IP end
    term Q port IC end
    term VCC end
    term GND end
  end
  gate SUPER_LOGIC cell LOGIC
    term A1 port A1 end
    term A2 port A2 end
    term A3 port A3 end
    term A4 port A4 end
    term A5 port A5 end
    term A6 port A6 end
    term B1 port B1 end
    term B2 port B2 end
    term C1 port C1 end
    term C2 port C2 end
    term D1 port D1 end
    term D2 port D2 end
    term E1 port E1 end
    term E2 port E2 end
    term F1 port F1 end
    term F2 port F2 end
    term F3 port F3 end
    term F4 port F4 end
    term F5 port F5 end
    term F6 port F6 end
    term MP port MP end
    term MS port MS end
    term NP port NP end
    term NS port NS end
    term OP port OP end
    term OS port OS end
    term PP port PP end
    term PS port PS end
    term QC port QC end
    term QR port QR end
    term QS port QS end
    term AZ port AZ end
    term FZ port FZ end
    term NZ port NZ end
    term OZ port OZ end
    term Q2Z port Q2Z end
    term QZ port QZ end
    term VCC end
    term GND end
  end
  gate DFF cell LOGIC
    term VCC port F5 port F3 port F1 port D1 port C1 port B1 port A5 port A3 port A1 end
    term GND port QR port F6 port F4 port F2 port E2 port D2 port C2 port B2 port A6 port A4 port A2 port QS end
    term CLK port QC end
    term D port E1 end
    term Q port QZ end
  end
  gate OUTPAD_25UM cell BIDIR
    term VCC port EQE port IE port OSEL port ESEL end
    term GND port IQC port IQE port IQR end
    term A port OQI end
    term P port IP end
  end
end
logical example_en_4bit
  gates 14
  nets 34
  gate I5.I1 master OUTPAD_25UM end
  gate I5.I2 master OUTPAD_25UM end
  gate I5.I3 master OUTPAD_25UM end
  gate I5.I4 master OUTPAD_25UM end
  gate I6 master INPAD_25UM end
  gate I7 master CKPAD_25UM end
  gate I8 master CKPAD_25UM end
  gate I9.QL1 master DFF end
  gate I9.QL2 master DFF end
  gate I9.QL3 master DFF end
  gate I9.QL4 master DFF end
  gate I10.I2 master SUPER_LOGIC end
  gate I11.I1 master SUPER_LOGIC end
  gate I11.I2 master SUPER_LOGIC end
  net VCC
    gate I11.I1 term E1 end
    gate I11.I2 term C1 end
    gate I11.I2 term A5 end
    gate I11.I2 term A3 end
    gate I11.I2 term A1 end
    gate I11.I1 term F5 end
    gate I10.I2 term PP end
    gate I10.I2 term F5 end
    gate I10.I2 term F3 end
    gate I10.I2 term F1 end
    gate I10.I2 term NS end
    gate I10.I2 term D1 end
    gate I10.I2 term C1 end
    gate I10.I2 term B1 end
    gate I10.I2 term MS end
    gate I10.I2 term OS end
    gate I10.I2 term A5 end
    gate I10.I2 term A3 end
    gate I10.I2 term A1 end
  end
  net GND
    gate I11.I1 term PP end
    gate I11.I1 term PS end
    gate I11.I1 term F6 end
    gate I11.I1 term F4 end
    gate I11.I1 term F2 end
    gate I11.I1 term NS end
    gate I11.I1 term D2 end
    gate I11.I1 term MP end
    gate I11.I1 term OP end
    gate I11.I1 term OS end
    gate I11.I1 term A6 end
    gate I11.I1 term A4 end
    gate I11.I1 term A2 end
    gate I11.I1 term QS end
    gate I11.I2 term PP end
    gate I11.I2 term PS end
    gate I11.I2 term F6 end
    gate I11.I2 term F4 end
    gate I11.I2 term F2 end
    gate I11.I2 term NP end
    gate I11.I2 term B2 end
    gate I11.I2 term MS end
    gate I11.I2 term OP end
    gate I11.I2 term OS end
    gate I11.I2 term A6 end
    gate I11.I2 term A4 end
    gate I11.I2 term A2 end
    gate I11.I2 term QS end
    gate I10.I2 term OP end
    gate I10.I2 term A6 end
    gate I10.I2 term A4 end
    gate I10.I2 term A2 end
    gate I10.I2 term QS end
    gate I10.I2 term MP end
    gate I10.I2 term B2 end
    gate I10.I2 term C2 end
    gate I10.I2 term D2 end
    gate I10.I2 term E2 end
    gate I10.I2 term NP end
    gate I10.I2 term F2 end
    gate I10.I2 term F4 end
    gate I10.I2 term F6 end
    gate I10.I2 term QR end
  end
  net clk
    gate I11.I2 term QC end
    gate I11.I1 term QC end
    gate I7 term Q end
    gate I10.I2 term QC end
    gate I9.QL1 term CLK end
    gate I9.QL2 term CLK end
    gate I9.QL3 term CLK end
    gate I9.QL4 term CLK end
  end
  net clear
    gate I8 term Q end
    gate I11.I2 term QR end
    gate I11.I1 term QR end
  end
  net enable
    gate I6 term Q end
    gate I10.I2 term E1 end
    gate I10.I2 term PS end
  end
  net count[3]
    gate I11.I2 term QZ end
    gate I11.I2 term B1 end
    gate I11.I2 term C2 end
    gate I11.I1 term A5 end
    gate I9.QL1 term D end
  end
  net count[2]
    gate I11.I2 term F1 end
    gate I11.I1 term D1 end
    gate I11.I1 term E2 end
    gate I11.I1 term Q2Z end
    gate I9.QL2 term D end
  end
  net count[1]
    gate I11.I1 term NP end
    gate I11.I2 term F3 end
    gate I11.I1 term MS end
    gate I11.I1 term B2 end
    gate I11.I1 term C1 end
    gate I11.I1 term QZ end
    gate I9.QL3 term D end
  end
  net count[0]
    gate I11.I2 term Q2Z end
    gate I11.I2 term D2 end
    gate I11.I2 term E1 end
    gate I11.I2 term F5 end
    gate I11.I1 term F3 end
    gate I11.I2 term NS end
    gate I9.QL4 term D end
  end
  net count_out[3] direction output
    gate I5.I4 term P end
  end
  net count_out[2] direction output
    gate I5.I3 term P end
  end
  net count_out[1] direction output
    gate I5.I2 term P end
  end
  net count_out[0] direction output
    gate I5.I1 term P end
  end
  net enable_in direction input
    gate I6 term P end
  end
  net clear_in direction input
    gate I8 term P end
  end
  net clk_in direction input
    gate I7 term P end
  end
  net count_reg[3]
    gate I5.I4 term A end
    gate I9.QL1 term Q end
  end
  net count_reg[2]
    gate I5.I3 term A end
    gate I9.QL2 term Q end
  end
  net count_reg[1]
    gate I5.I2 term A end
    gate I9.QL3 term Q end
  end
  net count_reg[0]
    gate I5.I1 term A end
    gate I9.QL4 term Q end
  end
  net enable_reg
    gate I10.I2 term QZ end
    gate I11.I2 term E2 end
    gate I11.I2 term D1 end
    gate I11.I2 term MP end
    gate I11.I1 term F1 end
  end
  net .I10-Q2 direction output
    gate I10.I2 term Q2Z end
  end
  net .I10.I2-AZ direction output
    gate I10.I2 term AZ end
  end
  net .I10.I2-OZ direction output
    gate I10.I2 term OZ end
  end
  net .I10.I2-NZ direction output
    gate I10.I2 term NZ end
  end
  net .I10.I2-FZ direction output
    gate I10.I2 term FZ end
  end
  net .I11-BCD_a
    gate I11.I1 term A1 end
    gate I11.I2 term FZ end
  end
  net .I11-enablehbit_a direction output
    gate I11.I1 term AZ end
  end
  net .I11-ED_a
    gate I11.I1 term C2 end
    gate I11.I1 term B1 end
    gate I11.I1 term A3 end
    gate I11.I1 term FZ end
  end
  net .I11.I1-OZ direction output
    gate I11.I1 term OZ end
  end
  net .I11.I1-NZ direction output
    gate I11.I1 term NZ end
  end
  net .I11.I2-AZ direction output
    gate I11.I2 term AZ end
  end
  net .I11.I2-OZ direction output
    gate I11.I2 term OZ end
  end
  net .I11.I2-NZ direction output
    gate I11.I2 term NZ end
  end
end