example_en_4bit.chp

VHDL examples for counter design, use QuickLogic eclips

    gate I5.I3 term ISEL end
    gate I5.I4 term SLEWRATE end
    gate I5.I4 term WPD end
    gate I5.I4 term ISEL end
    gate I6 term SLEWRATE end
    gate I6 term WPD end
    gate I6 term ISEL end
    gate I10.I2 term A1 end
    gate I10.I2 term A3 end
    gate I10.I2 term A5 end
    gate I10.I2 term B1 end
    gate I10.I2 term C1 end
    gate I10.I2 term D1 end
    gate I10.I2 term F1 end
    gate I10.I2 term F3 end
    gate I10.I2 term F5 end
    gate I10.I2 term MS end
    gate I10.I2 term NS end
    gate I10.I2 term OS end
    gate I10.I2 term PP end
    gate I11.I1 term E1 end
    gate I11.I1 term F5 end
    gate I11.I2 term A1 end
    gate I11.I2 term A3 end
    gate I11.I2 term A5 end
    gate I11.I2 term C1 end
  end
end
place up
  cell AG27
    block blockbuffer fragments A;
      port AZ net count[0]_LRBUF0
      port A1 net count[0]
    end
  end
  cell AI31
    gate I11.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term B1 port B1 end
      term C2 port C2 end
      term D1 port D1 end
      term D2 port D2 end
      term E1 port E1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term F5 port F5 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term FZ port FZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments FONQS;
      port FZ net .I11-BCD_a
      port Q2Z net count[0]
      port QZ net count[3]
      port DCLK net clk
      port CLKSEL net GND
      port B1 net count[3]
      port C2 net count[3]
      port D1 net enable_reg
      port D2 net count[0]
      port E1 net count[0]
      port E2 net enable_reg
      port F1 net count[2]
      port F3 net count[1]
      port F5 net count[0]
      port MP net enable_reg
      port MS net GND
      port NP net GND
      port NS net count[0]
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell AH32
    gate I9.QL1
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term Q port Q2Z end
    end
    block fragments S;
      port Q2Z net count_reg[3]
      port DCLK net clk
      port CLKSEL net GND
      port PS net count[3]
    end
  end
  cell AI32
    gate I11.I1
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term B1 port B1 end
      term B2 port B2 end
      term C1 port C1 end
      term C2 port C2 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PP port PP end
      term QR port QR end
      term FZ port FZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port FZ net .I11-ED_a
      port Q2Z net count[2]
      port QZ net count[1]
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I11-BCD_a
      port A3 net .I11-ED_a
      port A5 net count[3]
      port B1 net .I11-ED_a
      port B2 net count[1]
      port C1 net count[1]
      port C2 net .I11-ED_a
      port D1 net count[2]
      port E2 net count[2]
      port F1 net enable_reg
      port F3 net count[0]
      port MP net GND
      port MS net count[1]
      port NP net count[1]
      port NS net GND
      port OP net GND
      port OS net GND
      port PP net GND
      port QR net clear
    end
  end
  cell AJ32
    gate I10.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term QZ port Q2Z end
    end
    block fragments S;
      port Q2Z net enable_reg
      port DCLK net clk
      port CLKSEL net GND
      port PS net enable
    end
  end
  cell AK32
    gate I9.QL2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term Q port Q2Z end
    end
    block fragments S;
      port Q2Z net count_reg[2]
      port DCLK net clk
      port CLKSEL net GND
      port PS net count[2]
    end
  end
  cell AL32
    gate I9.QL3
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term Q port Q2Z end
    end
    block fragments S;
      port Q2Z net count_reg[1]
      port DCLK net clk
      port CLKSEL net GND
      port PS net count[1]
    end
  end
  cell AM32
    gate I9.QL4
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term Q port Q2Z end
    end
    block fragments S;
      port Q2Z net count_reg[0]
      port DCLK net clk
      port CLKSEL net GND
      port PS net count[0]_LRBUF0
    end
  end
  cell PLLIN2
    gate I8
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clear
      port IP net clear_in
    end
  end
  cell PLLIN0
    gate I7
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clk
      port IP net clk_in
    end
  end
  cell IO70
    gate I5.I4
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[3]
      port OQI net count_reg[3]
    end
  end
  cell IO77
    gate I6
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net enable
      port OQI net VCC
      port IE net GND
      port IP net enable_in
    end
  end
  cell IO79
    gate I5.I3
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[2]
      port OQI net count_reg[2]
    end
  end
  cell IO82
    gate I5.I2
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[1]
      port OQI net count_reg[1]
    end
  end
  cell IO84
    gate I5.I1
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[0]
      port OQI net count_reg[0]
    end
  end
end
route
  net clk
  wire AI31.DCLK port AI31.DCLK end
  wire AI32.DCLK port AI32.DCLK end
  wire AJ32.DCLK port AJ32.DCLK end
  wire AM32.DCLK port AM32.DCLK end
  wire AL32.DCLK port AL32.DCLK end
  wire AK32.DCLK port AK32.DCLK end
  wire AH32.DCLK port AH32.DCLK end
  wire V.36. 0.41 end
  wire V.39.42.41 end
  wire V.40. 0.41 end
  wire V.41.42.41 end
  wire V.38. 0.41 end
  wire V.37.42.41 end
  net clear
  wire AI31.QR port AI31.QR wire V.37.28.41 wire AI32.QR port AI32.QR end
  net enable
  wire AJ32.PS port AJ32.PS wire V.38.41.73 wire IO77.IZ port IO77.IZ end
  net count[3]
  wire AI31.C2 port AI31.C2 wire V.37.36.72 branch
    wire V.37.36.74 wire AI32.A5 port AI32.A5 end
    wire H.73.27.36 wire V.36.27.73 wire AH32.PS port AH32.PS end
    wire AI31.B1 port AI31.B1 end
    wire AI31.QZ port AI31.QZ end
  end
  net count[2]
  wire AI31.F1 port AI31.F1 wire V.37.33.71 wire V.37.33.73 branch
    wire AI32.E2 port AI32.E2 end
    wire H.73.29.36 wire H.73.29.38 wire V.39.39.73 wire AK32.PS port AK32.PS end
    wire AI32.D1 port AI32.D1 end
    wire AI32.Q2Z port AI32.Q2Z end
  end
  net count[1]
  wire AI31.F3 port AI31.F3 wire V.37.35.71 wire V.37.35.73 branch
    wire AI32.NP port AI32.NP end
    wire H.73.28.37 wire H.73.28.39 wire V.40.27.73 wire AL32.PS port AL32.PS end
    wire AI32.MS port AI32.MS end
    wire AI32.C1 port AI32.C1 end
    wire AI32.B2 port AI32.B2 end
    wire AI32.QZ port AI32.QZ end
  end
  net count[0]
  wire AG27.A1 port AG27.A1 wire V.35.36.64 wire H.65.30.35 wire V.36.41.65 wire H.71.29.36 wire V.37.37.71 branch
    wire V.37.37.73 wire AI32.F3 port AI32.F3 end
    wire AI31.NS port AI31.NS end
    wire AI31.F5 port AI31.F5 end
    wire AI31.E1 port AI31.E1 end
    wire AI31.D2 port AI31.D2 end
    wire AI31.Q2Z port AI31.Q2Z end
  end
  net count_reg[3]
  wire AH32.Q2Z port AH32.Q2Z wire V.36.41.73 wire IO70.OQI port IO70.OQI end
  net count_reg[2]
  wire AK32.Q2Z port AK32.Q2Z wire V.39. 9.73 wire IO79.OQI port IO79.OQI end
  net count_reg[1]
  wire AL32.Q2Z port AL32.Q2Z wire V.40.41.73 wire IO82.OQI port IO82.OQI end
  net count_reg[0]
  wire AM32.Q2Z port AM32.Q2Z wire V.41. 9.73 wire IO84.OQI port IO84.OQI end
  net enable_reg
  wire AI31.MP port AI31.MP wire V.37.38.72 branch
    wire V.37.38.74 wire AI32.F1 port AI32.F1 end
    wire AI31.E2 port AI31.E2 end
    wire AI31.D1 port AI31.D1 end
    wire H.73.30.37 wire V.38.27.73 wire AJ32.Q2Z port AJ32.Q2Z end
  end
  net .I11-BCD_a
  wire AI31.FZ port AI31.FZ wire V.37.39.71 wire V.37.39.73 wire AI32.A1 port AI32.A1 end
  net .I11-ED_a
  wire AI32.C2 port AI32.C2 wire V.37.21.73 branch
    wire AI32.B1 port AI32.B1 end
    wire AI32.A3 port AI32.A3 end
    wire AI32.FZ port AI32.FZ end
  end
  net count[0]_LRBUF0
  wire AM32.PS port AM32.PS wire V.41.11.67 wire H.67.29.40 wire H.67.29.38 wire H.67.29.36 wire H.67.29.34 wire V.35.38.66 wire V.35.38.64 wire AG27.AZ port AG27.AZ end
end
delay
    port AI31.DCLK  delay rise 0.146 fall 0.189 slew rise 0.389 fall 0.267 end
    port AI32.DCLK  delay rise 0.158 fall 0.200 slew rise 0.139 fall 0.227 end
    port AJ32.DCLK  delay rise 0.144 fall 0.192 slew rise 0.245 fall 0.247 end
    port AM32.DCLK  delay rise 0.131 fall 0.179 slew rise 0.245 fall 0.247 end
    port AL32.DCLK  delay rise 0.135 fall 0.183 slew rise 0.245 fall 0.247 end
    port AK32.DCLK  delay rise 0.140 fall 0.188 slew rise 0.245 fall 0.247 end
    port AH32.DCLK  delay rise 0.153 fall 0.200 slew rise 0.245 fall 0.247 end
    port AI31.QR  delay rise 0.185 fall 0.209 slew rise 0.306 fall 0.303 end
    port AI32.QR  delay rise 0.200 fall 0.224 slew rise 0.298 fall 0.321 end
    port AJ32.PS  delay rise 0.228 fall 0.206 slew rise 0.314 fall 0.259 end
    port AI31.C2  delay rise 0.260 fall 0.226 slew rise 0.462 fall 0.398 end
    port AI31.B1  delay rise 0.261 fall 0.227 slew rise 0.460 fall 0.397 end
    port AI32.A5  delay rise 0.290 fall 0.255 slew rise 0.405 fall 0.401 end
    port AH32.PS  delay rise 0.319 fall 0.283 slew rise 0.493 fall 0.390 end
    port AI31.F1  delay rise 0.315 fall 0.275 slew rise 0.504 fall 0.438 end
    port AI32.E2  delay rise 0.283 fall 0.244 slew rise 0.533 fall 0.375 end
    port AI32.D1  delay rise 0.284 fall 0.244 slew rise 0.532 fall 0.376 end
    port AK32.PS  delay rise 0.385 fall 0.343 slew rise 0.549 fall 0.391 end
    port AI31.F3  delay rise 0.368 fall 0.322 slew rise 0.591 fall 0.449 end
    port AI32.NP  delay rise 0.336 fall 0.291 slew rise 0.620 fall 0.519 end
    port AI32.MS  delay rise 0.336 fall 0.291 slew rise 0.620 fall 0.519 end
    port AI32.C1  delay rise 0.337 fall 0.292 slew rise 0.620 fall 0.518 end
    port AI32.B2  delay rise 0.336 fall 0.291 slew rise 0.620 fall 0.519 end
    port AL32.PS  delay rise 0.447 fall 0.398 slew rise 0.649 fall 0.410 end
    port AG27.A1  delay rise 0.606 fall 0.545 slew rise 0.815 fall 0.920 end
    port AI31.NS  delay rise 0.379 fall 0.325 slew rise 0.797 fall 0.697 end
    port AI31.F5  delay rise 0.379 fall 0.325 slew rise 0.797 fall 0.697 end
    port AI31.E1  delay rise 0.380 fall 0.326 slew rise 0.795 fall 0.695 end
    port AI31.D2  delay rise 0.379 fall 0.325 slew rise 0.797 fall 0.697 end
    port AI32.F3  delay rise 0.400 fall 0.346 slew rise 0.734 fall 0.647 end
    port IO70.OQI  delay rise 0.223 fall 0.204 slew rise 0.302 fall 0.213 end
    port IO79.OQI  delay rise 0.223 fall 0.204 slew rise 0.302 fall 0.213 end
    port IO82.OQI  delay rise 0.223 fall 0.204 slew rise 0.302 fall 0.213 end
    port IO84.OQI  delay rise 0.223 fall 0.204 slew rise 0.302 fall 0.213 end
    port AI31.MP  delay rise 0.358 fall 0.315 slew rise 0.518 fall 0.618 end
    port AI31.E2  delay rise 0.358 fall 0.315 slew rise 0.518 fall 0.618 end
    port AI31.D1  delay rise 0.359 fall 0.316 slew rise 0.518 fall 0.615 end
    port AI32.F1  delay rise 0.370 fall 0.327 slew rise 0.517 fall 0.574 end
    port AI32.A1  delay rise 0.149 fall 0.133 slew rise 0.181 fall 0.167 end
    port AI32.C2  delay rise 0.158 fall 0.141 slew rise 0.231 fall 0.196 end
    port AI32.B1  delay rise 0.159 fall 0.141 slew rise 0.230 fall 0.196 end
    port AI32.A3  delay rise 0.158 fall 0.141 slew rise 0.231 fall 0.196 end
    port AM32.PS  delay rise 0.657 fall 0.594 slew rise 1.021 fall 0.777 end
end