example_en_16bit_s.qcf

VHDL examples for counter design, use QuickLogic eclips

#QuickLogic Constraint file
#Automatically generated by SpDE version SpDE 9.5 Release Build2
#Date: 8/14/2003 at 16:05
window_in_placer  I9                           B2         C8


#-*-*-*- ************************************************* -*-*-*-

#-*-*-*-        DO NOT MANUALLY EDIT BELOW THIS LINE       -*-*-*-

#-*-*-*- ************************************************* -*-*-*-

#[Path constraints from the Path Analyzer]


#[Fixed Pin Placement]


#[Fixed FF Placement]


#[Fixed Ram Placement]


#[Fixed ECU Placement]


#[Pull FF]


#[Duplication constraints]


#[False Path Constraints]


#[Multi-Cycle Path Constraints]


#[Clock Constraints]


#[Frequency Constraints]


#[Point To Point Constraints]


#[Unused pads tie-off]
UnusedIO GND


#[Pin Standards ]


#[IOBank Standards]


#[IO SlewRate]


#[module name and window size for Window based placer]


#[routing priority for net(s)]
# Routing Priority for nets greater than 0 are only printed
# 0 -> Normal, 1 -> High, 2 -> Very High


#[Part Name]
partname ql8325


#[Package Name]
packname PS484