example_en_16bit_s.vhh

来自「VHDL examples for counter design, use Qu」· VHH 代码 · 共 8 行

entity example_en_16bit_s is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
             enable_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (15 downto 0) );
end example_en_16bit_s;