📄 example_en_32bit_s.vhd
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qc_r=>count_DUMMY(5), qd_r=>count_DUMMY(4) );
I19 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(7), A2=>gnd, A3=>count_DUMMY(6),
A4=>gnd, A5=>count_DUMMY(5), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>gnd, C2=>gnd, D1=>count_DUMMY(4), D2=>gnd, E1=>gnd,
E2=>gnd, F1=>enable, F2=>gnd, F3=>vcc, F4=>gnd, F5=>vcc,
F6=>gnd, MP=>gnd, MS=>gnd, NP=>gnd, \NS\=>gnd, OP=>vcc,
OS=>gnd, PP=>gnd, PS=>gnd, QC=>clk, QR=>clear, QS=>gnd,
AZ=>open, FZ=>enable_buf_a, NZ=>open, OZ=>open,
Q2Z=>open, QZ=>enable_2_r_DUMMY );
I14 : SUPER_LOGIC
Port Map ( A1=>count_DUMMY(3), A2=>gnd, A3=>count_DUMMY(2),
A4=>gnd, A5=>count_DUMMY(1), A6=>gnd, B1=>gnd, B2=>gnd,
C1=>gnd, C2=>gnd, D1=>count_DUMMY(0), D2=>gnd, E1=>vcc,
E2=>count_DUMMY(0), F1=>fo_enable_r_DUMMY, F2=>gnd,
F3=>enable, F4=>gnd, F5=>vcc, F6=>gnd, MP=>gnd, MS=>gnd,
NP=>gnd, \NS\=>enable_buf_a, OP=>vcc, OS=>gnd, PP=>gnd,
PS=>gnd, QC=>clk, QR=>clear, QS=>gnd, AZ=>open,
FZ=>enable_1_a, NZ=>open, OZ=>open, Q2Z=>open,
QZ=>fo_enable_r_DUMMY );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity COUNTER_EN_32BIT_S is
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (31 downto 0) );
end COUNTER_EN_32BIT_S;
architecture SCHEMATIC of COUNTER_EN_32BIT_S is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal enable_6 : STD_LOGIC;
signal enable_5 : STD_LOGIC;
signal enable_4 : STD_LOGIC;
signal enable_3 : STD_LOGIC;
signal enable_2 : STD_LOGIC;
signal enable_1 : STD_LOGIC;
signal count_DUMMY : STD_LOGIC_VECTOR (31 downto 0);
component COUNTER_EN_8BIT_IV_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
enable_3 : In STD_LOGIC;
enable_4 : In STD_LOGIC;
enable_5 : In STD_LOGIC;
enable_6 : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0) );
end component;
component COUNTER_EN_8BIT_III_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
enable_3 : In STD_LOGIC;
enable_4 : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_5_r : Out STD_LOGIC;
enable_6_r : Out STD_LOGIC );
end component;
component COUNTER_EN_8BIT_II_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
enable_1 : In STD_LOGIC;
enable_2 : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_3_r : Out STD_LOGIC;
enable_4_r : Out STD_LOGIC );
end component;
component COUNTER_EN_8BIT_I_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (7 downto 0);
enable_2_r : Out STD_LOGIC;
fo_enable_r : Out STD_LOGIC );
end component;
begin
count(31 downto 0) <= count_DUMMY(31 downto 0);
I9 : COUNTER_EN_8BIT_IV_S
Port Map ( clear=>clear, clk=>clk, enable=>enable,
enable_1=>enable_1, enable_2=>enable_2,
enable_3=>enable_3, enable_4=>enable_4,
enable_5=>enable_5, enable_6=>enable_6,
count(7 downto 0)=>count_DUMMY(31 downto 24) );
I10 : COUNTER_EN_8BIT_III_S
Port Map ( clear=>clear, clk=>clk, enable=>enable,
enable_1=>enable_1, enable_2=>enable_2,
enable_3=>enable_3, enable_4=>enable_4,
count(7 downto 0)=>count_DUMMY(23 downto 16),
enable_5_r=>enable_5, enable_6_r=>enable_6 );
I11 : COUNTER_EN_8BIT_II_S
Port Map ( clear=>clear, clk=>clk, enable=>enable,
enable_1=>enable_1, enable_2=>enable_2,
count(7 downto 0)=>count_DUMMY(15 downto 8),
enable_3_r=>enable_3, enable_4_r=>enable_4 );
I12 : COUNTER_EN_8BIT_I_S
Port Map ( clear=>clear, clk=>clk, enable=>enable,
count(7 downto 0)=>count_DUMMY(7 downto 0),
enable_2_r=>enable_2, fo_enable_r=>enable_1 );
end SCHEMATIC;
library IEEE;
use IEEE.std_logic_1164.all;
entity example_en_32bit_s is
Port ( clear_in : In STD_LOGIC;
clk_in : In STD_LOGIC;
enable_in : In STD_LOGIC;
count_out : Out STD_LOGIC_VECTOR (31 downto 0) );
end example_en_32bit_s;
architecture SCHEMATIC of example_en_32bit_s is
attribute syn_macro : integer;
attribute syn_macro of SCHEMATIC : architecture is 1;
signal count_reg : STD_LOGIC_VECTOR (31 downto 0);
signal count : STD_LOGIC_VECTOR (31 downto 0);
signal enable_reg : STD_LOGIC;
signal enable : STD_LOGIC;
signal clear : STD_LOGIC;
signal clk : STD_LOGIC;
signal count_out_DUMMY : STD_LOGIC_VECTOR (31 downto 0);
component COUNTER_EN_32BIT_S
Port ( clear : In STD_LOGIC;
clk : In STD_LOGIC;
enable : In STD_LOGIC;
count : Out STD_LOGIC_VECTOR (31 downto 0) );
end component;
component RG16_25UM
Port ( CLK : In STD_LOGIC;
D : In STD_LOGIC_VECTOR (15 downto 0);
Q : Out STD_LOGIC_VECTOR (15 downto 0) );
end component;
component DFF_2
Port ( CLK : In STD_LOGIC;
D1 : In STD_LOGIC;
D2 : In STD_LOGIC;
Q1 : Out STD_LOGIC;
Q2 : Out STD_LOGIC );
end component;
component OUTPAD_25UM
Port ( A : In STD_LOGIC;
P : Out STD_LOGIC );
end component;
component INPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
component CKPAD_25UM
Port ( P : In STD_LOGIC;
Q : Out STD_LOGIC );
end component;
begin
count_out(31 downto 0) <= count_out_DUMMY(31 downto 0);
I9 : COUNTER_EN_32BIT_S
Port Map ( clear=>clear, clk=>clk, enable=>enable_reg,
count(31 downto 0)=>count(31 downto 0) );
I1 : RG16_25UM
Port Map ( CLK=>clk, D(15 downto 0)=>count(15 downto 0),
Q(15 downto 0)=>count_reg(15 downto 0) );
I2 : RG16_25UM
Port Map ( CLK=>clk, D(15 downto 0)=>count(31 downto 16),
Q(15 downto 0)=>count_reg(31 downto 16) );
I3 : DFF_2
Port Map ( CLK=>clk, D1=>enable, D2=>enable, Q1=>enable_reg,
Q2=>open );
outpad_25umQ31Q : OUTPAD_25UM
Port Map ( A=>count_reg(31), P=>count_out_DUMMY(31) );
outpad_25umQ30Q : OUTPAD_25UM
Port Map ( A=>count_reg(30), P=>count_out_DUMMY(30) );
outpad_25umQ29Q : OUTPAD_25UM
Port Map ( A=>count_reg(29), P=>count_out_DUMMY(29) );
outpad_25umQ28Q : OUTPAD_25UM
Port Map ( A=>count_reg(28), P=>count_out_DUMMY(28) );
outpad_25umQ27Q : OUTPAD_25UM
Port Map ( A=>count_reg(27), P=>count_out_DUMMY(27) );
outpad_25umQ26Q : OUTPAD_25UM
Port Map ( A=>count_reg(26), P=>count_out_DUMMY(26) );
outpad_25umQ25Q : OUTPAD_25UM
Port Map ( A=>count_reg(25), P=>count_out_DUMMY(25) );
outpad_25umQ24Q : OUTPAD_25UM
Port Map ( A=>count_reg(24), P=>count_out_DUMMY(24) );
outpad_25umQ23Q : OUTPAD_25UM
Port Map ( A=>count_reg(23), P=>count_out_DUMMY(23) );
outpad_25umQ22Q : OUTPAD_25UM
Port Map ( A=>count_reg(22), P=>count_out_DUMMY(22) );
outpad_25umQ21Q : OUTPAD_25UM
Port Map ( A=>count_reg(21), P=>count_out_DUMMY(21) );
outpad_25umQ20Q : OUTPAD_25UM
Port Map ( A=>count_reg(20), P=>count_out_DUMMY(20) );
outpad_25umQ19Q : OUTPAD_25UM
Port Map ( A=>count_reg(19), P=>count_out_DUMMY(19) );
outpad_25umQ18Q : OUTPAD_25UM
Port Map ( A=>count_reg(18), P=>count_out_DUMMY(18) );
outpad_25umQ17Q : OUTPAD_25UM
Port Map ( A=>count_reg(17), P=>count_out_DUMMY(17) );
outpad_25umQ16Q : OUTPAD_25UM
Port Map ( A=>count_reg(16), P=>count_out_DUMMY(16) );
outpad_25umQ15Q : OUTPAD_25UM
Port Map ( A=>count_reg(15), P=>count_out_DUMMY(15) );
outpad_25umQ14Q : OUTPAD_25UM
Port Map ( A=>count_reg(14), P=>count_out_DUMMY(14) );
outpad_25umQ13Q : OUTPAD_25UM
Port Map ( A=>count_reg(13), P=>count_out_DUMMY(13) );
outpad_25umQ12Q : OUTPAD_25UM
Port Map ( A=>count_reg(12), P=>count_out_DUMMY(12) );
outpad_25umQ11Q : OUTPAD_25UM
Port Map ( A=>count_reg(11), P=>count_out_DUMMY(11) );
outpad_25umQ10Q : OUTPAD_25UM
Port Map ( A=>count_reg(10), P=>count_out_DUMMY(10) );
outpad_25umQ9Q : OUTPAD_25UM
Port Map ( A=>count_reg(9), P=>count_out_DUMMY(9) );
outpad_25umQ8Q : OUTPAD_25UM
Port Map ( A=>count_reg(8), P=>count_out_DUMMY(8) );
outpad_25umQ7Q : OUTPAD_25UM
Port Map ( A=>count_reg(7), P=>count_out_DUMMY(7) );
outpad_25umQ6Q : OUTPAD_25UM
Port Map ( A=>count_reg(6), P=>count_out_DUMMY(6) );
outpad_25umQ5Q : OUTPAD_25UM
Port Map ( A=>count_reg(5), P=>count_out_DUMMY(5) );
outpad_25umQ4Q : OUTPAD_25UM
Port Map ( A=>count_reg(4), P=>count_out_DUMMY(4) );
outpad_25umQ3Q : OUTPAD_25UM
Port Map ( A=>count_reg(3), P=>count_out_DUMMY(3) );
outpad_25umQ2Q : OUTPAD_25UM
Port Map ( A=>count_reg(2), P=>count_out_DUMMY(2) );
outpad_25umQ1Q : OUTPAD_25UM
Port Map ( A=>count_reg(1), P=>count_out_DUMMY(1) );
outpad_25umQ0Q : OUTPAD_25UM
Port Map ( A=>count_reg(0), P=>count_out_DUMMY(0) );
I4 : INPAD_25UM
Port Map ( P=>enable_in, Q=>enable );
I5 : CKPAD_25UM
Port Map ( P=>clear_in, Q=>clear );
I6 : CKPAD_25UM
Port Map ( P=>clk_in, Q=>clk );
end SCHEMATIC;
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