example_4bit_load.qdf

VHDL examples for counter design, use QuickLogic eclips

    gate I1.I4.I2 term E2 end
    gate I1.I4.I2 term NP end
    gate I1.I4.I2 term F2 end
    gate I1.I4.I2 term F4 end
    gate I1.I4.I2 term F6 end
    gate I1.I4.I2 term QR end
    gate I1.I3.I2 term OP end
    gate I1.I3.I2 term A6 end
    gate I1.I3.I2 term A4 end
    gate I1.I3.I2 term A2 end
    gate I1.I3.I2 term QS end
    gate I1.I3.I2 term MP end
    gate I1.I3.I2 term B2 end
    gate I1.I3.I2 term C2 end
    gate I1.I3.I2 term D2 end
    gate I1.I3.I2 term E2 end
    gate I1.I3.I2 term NP end
    gate I1.I3.I2 term F2 end
    gate I1.I3.I2 term F4 end
    gate I1.I3.I2 term F6 end
    gate I1.I3.I2 term QR end
  end
  net clk
    gate I12.I3 term QC end
    gate I12.I18 term QC end
    gate I12.I16 term QC end
    gate I12.I17 term QC end
    gate I3.I2 term QC end
    gate I2.I3.I2 term QC end
    gate I2.I4.I2 term QC end
    gate I9 term Q end
    gate I1.I3.I2 term QC end
    gate I1.I4.I2 term QC end
  end
  net clear
    gate I12.I3 term QR end
    gate I12.I18 term QR end
    gate I12.I16 term QR end
    gate I12.I17 term QR end
    gate I8 term Q end
  end
  net enable
    gate I3.I2 term E1 end
    gate I7 term Q end
  end
  net load
    gate I3.I2 term PS end
    gate I6 term Q end
  end
  net data_in[3]
    gate I1.I3.I2 term PS end
    gate I5.I1 term Q end
  end
  net data_in[2]
    gate I1.I3.I2 term E1 end
    gate I5.I2 term Q end
  end
  net data_in[1]
    gate I1.I4.I2 term PS end
    gate I5.I3 term Q end
  end
  net data_in[0]
    gate I1.I4.I2 term E1 end
    gate I5.I4 term Q end
  end
  net count[3]
    gate I2.I3.I2 term PS end
    gate I12.I16 term Q2Z end
  end
  net count[2]
    gate I2.I3.I2 term E1 end
    gate I12.I17 term Q2Z end
  end
  net count[1]
    gate I2.I4.I2 term PS end
    gate I12.I18 term Q2Z end
  end
  net count[0]
    gate I2.I4.I2 term E1 end
    gate I12.I3 term Q2Z end
    gate I12.I3 term D1 end
    gate I12.I3 term E2 end
    gate I12.I18 term F1 end
  end
  net enable_reg
    gate I3.I2 term QZ end
    gate I12.I18 term A1 end
  end
  net load_reg
    gate I3.I2 term Q2Z end
    gate I12.I3 term A2 end
  end
  net data_in_reg[3]
    gate I1.I3.I2 term Q2Z end
    gate I12.I16 term B1 end
  end
  net data_in_reg[2]
    gate I1.I3.I2 term QZ end
    gate I12.I17 term B1 end
  end
  net data_in_reg[1]
    gate I1.I4.I2 term Q2Z end
    gate I12.I18 term B1 end
  end
  net data_in_reg[0]
    gate I1.I4.I2 term QZ end
    gate I12.I3 term B1 end
  end
  net count_reg[3]
    gate I2.I3.I2 term Q2Z end
    gate I4.I4 term A end
  end
  net count_reg[2]
    gate I2.I3.I2 term QZ end
    gate I4.I3 term A end
  end
  net count_reg[1]
    gate I2.I4.I2 term Q2Z end
    gate I4.I2 term A end
  end
  net count_reg[0]
    gate I2.I4.I2 term QZ end
    gate I4.I1 term A end
  end
  net count_out[3] direction output
    gate I4.I4 term P end
  end
  net count_out[2] direction output
    gate I4.I3 term P end
  end
  net count_out[1] direction output
    gate I4.I2 term P end
  end
  net count_out[0] direction output
    gate I4.I1 term P end
  end
  net clk_in direction input
    gate I9 term P end
  end
  net clear_in direction input
    gate I8 term P end
  end
  net enable_in direction input
    gate I7 term P end
  end
  net load_in direction input
    gate I6 term P end
  end
  net data[3] direction input
    gate I5.I1 term P end
  end
  net data[2] direction input
    gate I5.I2 term P end
  end
  net data[1] direction input
    gate I5.I3 term P end
  end
  net data[0] direction input
    gate I5.I4 term P end
  end
  net .I1.I3.I2-AZ direction output
    gate I1.I3.I2 term AZ end
  end
  net .I1.I3.I2-OZ direction output
    gate I1.I3.I2 term OZ end
  end
  net .I1.I3.I2-NZ direction output
    gate I1.I3.I2 term NZ end
  end
  net .I1.I3.I2-FZ direction output
    gate I1.I3.I2 term FZ end
  end
  net .I1.I4.I2-AZ direction output
    gate I1.I4.I2 term AZ end
  end
  net .I1.I4.I2-OZ direction output
    gate I1.I4.I2 term OZ end
  end
  net .I1.I4.I2-NZ direction output
    gate I1.I4.I2 term NZ end
  end
  net .I1.I4.I2-FZ direction output
    gate I1.I4.I2 term FZ end
  end
  net .I2.I3.I2-AZ direction output
    gate I2.I3.I2 term AZ end
  end
  net .I2.I3.I2-OZ direction output
    gate I2.I3.I2 term OZ end
  end
  net .I2.I3.I2-NZ direction output
    gate I2.I3.I2 term NZ end
  end
  net .I2.I3.I2-FZ direction output
    gate I2.I3.I2 term FZ end
  end
  net .I2.I4.I2-AZ direction output
    gate I2.I4.I2 term AZ end
  end
  net .I2.I4.I2-OZ direction output
    gate I2.I4.I2 term OZ end
  end
  net .I2.I4.I2-NZ direction output
    gate I2.I4.I2 term NZ end
  end
  net .I2.I4.I2-FZ direction output
    gate I2.I4.I2 term FZ end
  end
  net .I3.I2-AZ direction output
    gate I3.I2 term AZ end
  end
  net .I3.I2-OZ direction output
    gate I3.I2 term OZ end
  end
  net .I3.I2-NZ direction output
    gate I3.I2 term NZ end
  end
  net .I3.I2-FZ direction output
    gate I3.I2 term FZ end
  end
  net .I12-load_N
    gate I12.I3 term AZ end
    gate I12.I18 term OS end
    gate I12.I16 term OS end
    gate I12.I17 term OS end
  end
  net .I12-Qd_a
    gate I12.I3 term OZ end
    gate I12.I3 term PS end
  end
  net .I12-Qd_r
    gate I12.I3 term QZ end
    gate I12.I16 term F5 end
    gate I12.I17 term F3 end
  end
  net .I12-enable_buf
    gate I12.I18 term AZ end
    gate I12.I3 term NP end
    gate I12.I18 term NP end
    gate I12.I16 term NP end
    gate I12.I17 term NP end
  end
  net .I12-Qc_r
    gate I12.I17 term F1 end
    gate I12.I16 term F3 end
    gate I12.I18 term E2 end
    gate I12.I18 term D1 end
    gate I12.I18 term QZ end
  end
  net .I12-Qc_a
    gate I12.I18 term OZ end
    gate I12.I18 term PS end
  end
  net .I12-Qa_a
    gate I12.I16 term OZ end
    gate I12.I16 term PS end
  end
  net .I12-Qb_a
    gate I12.I17 term OZ end
    gate I12.I17 term PS end
  end
  net .I12-Qa_r
    gate I12.I16 term QZ end
    gate I12.I16 term D1 end
    gate I12.I16 term E2 end
  end
  net .I12-Qb_r
    gate I12.I17 term QZ end
    gate I12.I17 term D1 end
    gate I12.I17 term E2 end
    gate I12.I16 term F1 end
  end
  net .I12.I3-NZ direction output
    gate I12.I3 term NZ end
  end
  net .I12.I3-FZ direction output
    gate I12.I3 term FZ end
  end
  net .I12.I16-AZ direction output
    gate I12.I16 term AZ end
  end
  net .I12.I16-NZ direction output
    gate I12.I16 term NZ end
  end
  net .I12.I16-FZ direction output
    gate I12.I16 term FZ end
  end
  net .I12.I17-AZ direction output
    gate I12.I17 term AZ end
  end
  net .I12.I17-NZ direction output
    gate I12.I17 term NZ end
  end
  net .I12.I17-FZ direction output
    gate I12.I17 term FZ end
  end
  net .I12.I18-NZ direction output
    gate I12.I18 term NZ end
  end
  net .I12.I18-FZ direction output
    gate I12.I18 term FZ end
  end
end