example_4bit_load.chp

VHDL examples for counter design, use QuickLogic eclips

      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term AZ port AZ end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I12-enable_buf
      port OZ net .I12-Qc_a
      port Q2Z net count[1]
      port QZ net .I12-Qc_r
      port DCLK net clk
      port CLKSEL net GND
      port A1 net enable_reg
      port B1 net data_in_reg[1]
      port C1 net GND
      port D1 net .I12-Qc_r
      port E2 net .I12-Qc_r
      port F1 net count[0]
      port MP net GND
      port MS net GND
      port NP net .I12-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12-load_N
      port PS net .I12-Qc_a
      port QR net clear
    end
  end
  cell C4
    gate I12.I17
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments FONQS;
      port OZ net .I12-Qb_a
      port Q2Z net count[2]
      port QZ net .I12-Qb_r
      port DCLK net clk
      port CLKSEL net GND
      port B1 net data_in_reg[2]
      port C1 net GND
      port D1 net .I12-Qb_r
      port E2 net .I12-Qb_r
      port F1 net .I12-Qc_r
      port F3 net .I12-Qd_r
      port MP net GND
      port MS net GND
      port NP net .I12-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12-load_N
      port PS net .I12-Qb_a
      port QR net clear
    end
  end
  cell B5
    gate I3.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net load_reg
      port QZ net enable_reg
      port DCLK net clk
      port CLKSEL net GND
      port E1 net enable
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net load
    end
  end
  cell A6
    gate I2.I3.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[3]
      port QZ net count_reg[2]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[2]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[3]
    end
  end
  cell PLLIN2
    gate I8
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clear
      port IP net clear_in
    end
  end
  cell PLLIN0
    gate I9
      term P port IP end
      term Q port IC end
    end
    block fragments P;
      port IC net clk
      port IP net clk_in
    end
  end
  cell IO275
    gate I5.I2
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net data_in[2]
      port OQI net VCC
      port IE net GND
      port IP net data[2]
    end
  end
  cell IO276
    gate I5.I1
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net data_in[3]
      port OQI net VCC
      port IE net GND
      port IP net data[3]
    end
  end
  cell IO287
    gate I4.I1
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[0]
      port OQI net count_reg[0]
    end
  end
  cell IO288
    gate I4.I2
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[1]
      port OQI net count_reg[1]
    end
  end
  cell IO289
    gate I5.I3
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net data_in[1]
      port OQI net VCC
      port IE net GND
      port IP net data[1]
    end
  end
  cell IO290
    gate I5.I4
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net data_in[0]
      port OQI net VCC
      port IE net GND
      port IP net data[0]
    end
  end
  cell IO291
    gate I6
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net load
      port OQI net VCC
      port IE net GND
      port IP net load_in
    end
  end
  cell IO292
    gate I7
      term VCC port OQI end
      term GND port IE end
      term P port IP end
      term Q port IZ end
    end
    block fragments P;
      port IZ net enable
      port OQI net VCC
      port IE net GND
      port IP net enable_in
    end
  end
  cell IO293
    gate I4.I4
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[3]
      port OQI net count_reg[3]
    end
  end
  cell IO297
    gate I4.I3
      term A port OQI end
      term P port IP end
    end
    block fragments P;
      port IP net count_out[2]
      port OQI net count_reg[2]
    end
  end
end
route
  net clk
  wire B4.DCLK port B4.DCLK end
  wire C4.DCLK port C4.DCLK end
  wire C3.DCLK port C3.DCLK end
  wire B3.DCLK port B3.DCLK end
  wire B5.DCLK port B5.DCLK end
  wire A3.DCLK port A3.DCLK end
  wire A6.DCLK port A6.DCLK end
  wire A4.DCLK port A4.DCLK end
  wire C1.DCLK port C1.DCLK end
  wire V. 1.42. 0 end
  wire V. 3.42. 0 end
  wire V. 2. 0. 0 end
  net clear
  wire B4.QR port B4.QR wire V. 2.14. 0 wire B3.QR port B3.QR end
  wire C4.QR port C4.QR wire V. 3.28. 0 wire C3.QR port C3.QR end
  net enable
  wire IO292.IZ port IO292.IZ wire H.15.28. 0 wire V. 2.26.14 wire B5.E1 port B5.E1 end
  net load
  wire IO291.IZ port IO291.IZ wire H.15.30. 0 wire V. 2.28.14 wire B5.PS port B5.PS end
  net data_in[3]
  wire IO276.IZ port IO276.IZ wire V. 3.37. 0 wire V. 3.37. 3 wire C1.PS port C1.PS end
  net data_in[2]
  wire IO275.IZ port IO275.IZ wire V. 3.39. 0 wire V. 3.39. 3 wire C1.E1 port C1.E1 end
  net data_in[1]
  wire IO289.IZ port IO289.IZ wire H.13.13. 0 wire V. 1.34.12 wire A4.PS port A4.PS end
  net data_in[0]
  wire IO290.IZ port IO290.IZ wire H.13.27. 0 wire V. 1.36.12 wire A4.E1 port A4.E1 end
  net count[3]
  wire C3.Q2Z port C3.Q2Z wire V. 3.15. 9 wire H. 9.29. 2 wire H. 9.29. 0 wire V. 1.10. 9 wire A6.PS port A6.PS end
  net count[2]
  wire C4.Q2Z port C4.Q2Z wire V. 3.36.12 wire H.13.29. 2 wire H.13.29. 0 wire V. 1.39.13 wire V. 1.39.15 wire A6.E1 port A6.E1 end
  net count[1]
  wire B4.Q2Z port B4.Q2Z wire V. 2. 7.11 wire H.11.28. 0 wire V. 1.34.10 wire A3.PS port A3.PS end
  net count[0]
  wire B4.F1 port B4.F1 wire V. 2.23.11 wire V. 2.23. 9 branch
    wire B3.E2 port B3.E2 end
    wire H. 9.30. 0 wire V. 1.39. 9 wire A3.E1 port A3.E1 end
    wire B3.D1 port B3.D1 end
    wire B3.Q2Z port B3.Q2Z end
  end
  net enable_reg
  wire B4.A1 port B4.A1 wire V. 2. 9.11 wire V. 2. 9.13 wire B5.QZ port B5.QZ end
  net load_reg
  wire B3.A2 port B3.A2 wire V. 2.42. 7 wire B5.Q2Z port B5.Q2Z end
  net data_in_reg[3]
  wire C3.B1 port C3.B1 wire V. 3.36.10 wire V. 3.36. 8 wire V. 3.36. 6 wire C1.Q2Z port C1.Q2Z end
  net data_in_reg[2]
  wire C4.B1 port C4.B1 wire V. 3.38.12 wire V. 3.38.10 wire V. 3.38. 8 wire V. 3.38. 6 wire C1.QZ port C1.QZ end
  net data_in_reg[1]
  wire B4.B1 port B4.B1 wire V. 2.28.12 wire H.13.30. 0 wire V. 1.38.12 wire A4.Q2Z port A4.Q2Z end
  net data_in_reg[0]
  wire B3.B1 port B3.B1 wire V. 2.24.10 wire H.11.30. 0 wire V. 1.39.11 wire A4.QZ port A4.QZ end
  net count_reg[3]
  wire IO293.OQI port IO293.OQI wire H.17.27. 0 wire V. 1.36.16 wire A6.Q2Z port A6.Q2Z end
  net count_reg[2]
  wire IO297.OQI port IO297.OQI wire H.17.29. 0 wire V. 1.38.16 wire A6.QZ port A6.QZ end
  net count_reg[1]
  wire IO288.OQI port IO288.OQI wire H.11.27. 0 wire V. 1.36.10 wire A3.Q2Z port A3.Q2Z end
  net count_reg[0]
  wire IO287.OQI port IO287.OQI wire H.11.29. 0 wire V. 1.38.10 wire A3.QZ port A3.QZ end
  net .I12-load_N
  wire B4.OS port B4.OS wire V. 2.26.12 wire V. 2.26.10 branch
    wire H.11.11. 2 wire V. 3.17.11 branch
      wire C4.OS port C4.OS end
      wire V. 3.17. 9 wire C3.OS port C3.OS end
    end
    wire B3.AZ port B3.AZ end
  end
  net .I12-Qd_a
  wire B3.PS port B3.PS wire V. 2.25. 9 wire B3.OZ port B3.OZ end
  net .I12-Qd_r
  wire C4.F3 port C4.F3 wire V. 3.19.11 branch
    wire V. 3.19. 9 wire C3.F5 port C3.F5 end
    wire H.11.13. 2 wire V. 2.28.10 wire B3.QZ port B3.QZ end
  end
  net .I12-enable_buf
  wire B4.NP port B4.NP wire V. 2.27.11 branch
    wire V. 2.27. 9 wire B3.NP port B3.NP end
    wire H.11.27. 2 wire V. 3.21.11 branch
      wire C4.NP port C4.NP end
      wire V. 3.21. 9 wire C3.NP port C3.NP end
    end
    wire B4.AZ port B4.AZ end
  end
  net .I12-Qc_r
  wire B4.E2 port B4.E2 wire V. 2.21.11 branch
    wire H.11.29. 2 wire V. 3.33.11 branch
      wire C4.F1 port C4.F1 end
      wire V. 3.33. 9 wire C3.F3 port C3.F3 end
    end
    wire B4.D1 port B4.D1 end
    wire B4.QZ port B4.QZ end
  end
  net .I12-Qc_a
  wire B4.PS port B4.PS wire V. 2.25.11 wire B4.OZ port B4.OZ end
  net .I12-Qa_a
  wire C3.PS port C3.PS wire V. 3.35. 9 wire C3.OZ port C3.OZ end
  net .I12-Qb_a
  wire C4.PS port C4.PS wire V. 3.37.11 wire C4.OZ port C4.OZ end
  net .I12-Qa_r
  wire C3.E2 port C3.E2 wire V. 3.37. 9 branch
    wire C3.D1 port C3.D1 end
    wire C3.QZ port C3.QZ end
  end
  net .I12-Qb_r
  wire C4.E2 port C4.E2 wire V. 3.39.11 branch
    wire V. 3.39. 9 wire C3.F1 port C3.F1 end
    wire C4.D1 port C4.D1 end
    wire C4.QZ port C4.QZ end
  end
end
delay
    port B4.DCLK  delay rise 0.175 fall 0.222 slew rise 0.228 fall 0.281 end
    port C4.DCLK  delay rise 0.171 fall 0.216 slew rise 0.176 fall 0.252 end
    port C3.DCLK  delay rise 0.191 fall 0.235 slew rise 0.263 fall 0.311 end
    port B3.DCLK  delay rise 0.194 fall 0.240 slew rise 0.253 fall 0.325 end
    port B5.DCLK  delay rise 0.156 fall 0.203 slew rise 0.218 fall 0.299 end
    port A3.DCLK  delay rise 0.199 fall 0.245 slew rise 0.281 fall 0.288 end
    port A6.DCLK  delay rise 0.144 fall 0.188 slew rise 0.203 fall 0.224 end
    port A4.DCLK  delay rise 0.181 fall 0.226 slew rise 0.246 fall 0.264 end
    port C1.DCLK  delay rise 0.226 fall 0.269 slew rise 0.247 fall 0.320 end
    port B4.QR  delay rise 0.204 fall 0.229 slew rise 0.343 fall 0.360 end
    port C4.QR  delay rise 0.199 fall 0.225 slew rise 0.343 fall 0.360 end
    port C3.QR  delay rise 0.222 fall 0.247 slew rise 0.348 fall 0.358 end
    port B3.QR  delay rise 0.226 fall 0.251 slew rise 0.348 fall 0.358 end
    port B5.E1  delay rise 0.186 fall 0.167 slew rise 0.256 fall 0.223 end
    port B5.PS  delay rise 0.182 fall 0.164 slew rise 0.251 fall 0.212 end
    port C1.PS  delay rise 0.346 fall 0.316 slew rise 0.438 fall 0.370 end
    port C1.E1  delay rise 0.351 fall 0.321 slew rise 0.522 fall 0.381 end
    port A4.PS  delay rise 0.165 fall 0.148 slew rise 0.237 fall 0.204 end
    port A4.E1  delay rise 0.168 fall 0.151 slew rise 0.238 fall 0.207 end
    port A6.PS  delay rise 0.377 fall 0.339 slew rise 0.502 fall 0.413 end
    port A6.E1  delay rise 0.356 fall 0.318 slew rise 0.497 fall 0.413 end
    port A3.PS  delay rise 0.233 fall 0.208 slew rise 0.332 fall 0.244 end
    port B4.F1  delay rise 0.304 fall 0.267 slew rise 0.441 fall 0.418 end
    port B3.E2  delay rise 0.282 fall 0.246 slew rise 0.490 fall 0.423 end
    port B3.D1  delay rise 0.283 fall 0.247 slew rise 0.489 fall 0.423 end
    port A3.E1  delay rise 0.348 fall 0.311 slew rise 0.517 fall 0.400 end
    port B4.A1  delay rise 0.150 fall 0.134 slew rise 0.188 fall 0.172 end
    port B3.A2  delay rise 0.163 fall 0.147 slew rise 0.213 fall 0.203 end
    port C3.B1  delay rise 0.207 fall 0.184 slew rise 0.278 fall 0.224 end
    port C4.B1  delay rise 0.269 fall 0.239 slew rise 0.341 fall 0.304 end
    port B4.B1  delay rise 0.236 fall 0.211 slew rise 0.333 fall 0.274 end
    port B3.B1  delay rise 0.236 fall 0.211 slew rise 0.333 fall 0.274 end
    port IO293.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO297.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO288.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port IO287.OQI  delay rise 0.167 fall 0.151 slew rise 0.216 fall 0.208 end
    port B4.OS  delay rise 0.272 fall 0.234 slew rise 0.446 fall 0.401 end
    port C4.OS  delay rise 0.339 fall 0.299 slew rise 0.519 fall 0.375 end
    port C3.OS  delay rise 0.355 fall 0.314 slew rise 0.501 fall 0.620 end
    port B3.PS  delay rise 0.105 fall 0.094 slew rise 0.123 fall 0.117 end
    port C4.F3  delay rise 0.280 fall 0.247 slew rise 0.410 fall 0.359 end
    port C3.F5  delay rise 0.295 fall 0.261 slew rise 0.396 fall 0.350 end
    port B4.NP  delay rise 0.267 fall 0.228 slew rise 0.525 fall 0.468 end
    port C4.NP  delay rise 0.367 fall 0.324 slew rise 0.572 fall 0.406 end
    port C3.NP  delay rise 0.383 fall 0.339 slew rise 0.550 fall 0.426 end
    port B3.NP  delay rise 0.301 fall 0.261 slew rise 0.488 fall 0.454 end
    port B4.E2  delay rise 0.242 fall 0.207 slew rise 0.501 fall 0.378 end
    port B4.D1  delay rise 0.242 fall 0.208 slew rise 0.500 fall 0.378 end
    port C4.F1  delay rise 0.339 fall 0.300 slew rise 0.501 fall 0.340 end
    port C3.F3  delay rise 0.354 fall 0.315 slew rise 0.473 fall 0.391 end
    port B4.PS  delay rise 0.105 fall 0.094 slew rise 0.123 fall 0.117 end
    port C3.PS  delay rise 0.105 fall 0.094 slew rise 0.123 fall 0.117 end
    port C4.PS  delay rise 0.105 fall 0.094 slew rise 0.123 fall 0.117 end
    port C3.E2  delay rise 0.132 fall 0.118 slew rise 0.203 fall 0.153 end
    port C3.D1  delay rise 0.133 fall 0.119 slew rise 0.202 fall 0.154 end
    port C4.E2  delay rise 0.182 fall 0.160 slew rise 0.307 fall 0.237 end
    port C4.D1  delay rise 0.183 fall 0.161 slew rise 0.306 fall 0.237 end
    port C3.F1  delay rise 0.205 fall 0.183 slew rise 0.275 fall 0.242 end
end