example_4bit_load.chp

VHDL examples for counter design, use QuickLogic eclips

    term WD[5] port WD5 end
    term WD[4] port WD4 end
    term WD[3] port WD3 end
    term WD[2] port WD2 end
    term WD[1] port WD1 end
    term WD[0] port WD0 end
    term ASYNCRD port ASYNCRD end
    term RD[17] port RD17 end
    term RD[16] port RD16 end
    term RD[15] port RD15 end
    term RD[14] port RD14 end
    term RD[13] port RD13 end
    term RD[12] port RD12 end
    term RD[11] port RD11 end
    term RD[10] port RD10 end
    term RD[9] port RD9 end
    term RD[8] port RD8 end
    term RD[7] port RD7 end
    term RD[6] port RD6 end
    term RD[5] port RD5 end
    term RD[4] port RD4 end
    term RD[3] port RD3 end
    term RD[2] port RD2 end
    term RD[1] port RD1 end
    term RD[0] port RD0 end
    term GND port WA9 port WA8 port WA7 port RA9 port RA8 port RA7 port MODE1 port MODE0 end
    term VCC end
  end
  gate ECU cell QMATH
    term SIGN2 port SIGN2 end
    term SIGN1 port SIGN1 end
    term RESET port RESET end
    term CLK port CLK end
    term A[15] port A15 end
    term A[14] port A14 end
    term A[13] port A13 end
    term A[12] port A12 end
    term A[11] port A11 end
    term A[10] port A10 end
    term A[9] port A9 end
    term A[8] port A8 end
    term A[7] port A7 end
    term A[6] port A6 end
    term A[5] port A5 end
    term A[4] port A4 end
    term A[3] port A3 end
    term A[2] port A2 end
    term A[1] port A1 end
    term A[0] port A0 end
    term B[15] port B15 end
    term B[14] port B14 end
    term B[13] port B13 end
    term B[12] port B12 end
    term B[11] port B11 end
    term B[10] port B10 end
    term B[9] port B9 end
    term B[8] port B8 end
    term B[7] port B7 end
    term B[6] port B6 end
    term B[5] port B5 end
    term B[4] port B4 end
    term B[3] port B3 end
    term B[2] port B2 end
    term B[1] port B1 end
    term B[0] port B0 end
    term S3 port S3 end
    term S2 port S2 end
    term S1 port S1 end
    term CIN port CIN end
    term Q[16] port OUT16 end
    term Q[15] port OUT15 end
    term Q[14] port OUT14 end
    term Q[13] port OUT13 end
    term Q[12] port OUT12 end
    term Q[11] port OUT11 end
    term Q[10] port OUT10 end
    term Q[9] port OUT9 end
    term Q[8] port OUT8 end
    term Q[7] port OUT7 end
    term Q[6] port OUT6 end
    term Q[5] port OUT5 end
    term Q[4] port OUT4 end
    term Q[3] port OUT3 end
    term Q[2] port OUT2 end
    term Q[1] port OUT1 end
    term Q[0] port OUT0 end
    term GND end
    term VCC end
  end
  gate PLL_TOP cell PLL
    term S4 port S4 end
    term S3 port S3 end
    term S2 port S2 end
    term S1 port S1 end
    term LOCK_DETECTn port LD end
    term PLLCLK_NET port PLLCK end
    term CLKPAD_OUT port PLLOUT end
    term PLL_RESET port PLLRST end
    term PLLCLK_IN port PLLIN end
    term GND end
    term VCC end
  end
  gate PLL_OUTPAD_25UM cell PLLOUTPAD
    term S port SEL end
    term P port IP end
    term A port IZ end
    term GND end
    term VCC end
  end
  gate PLL_RSTPAD_25UM cell PLLRSTPAD
    term Q port IZ end
    term P port IP end
    term GND end
    term VCC end
  end
  gate PLL_CLKPAD_25UM cell CLOCK
    term O port OP end
    term Q port IC end
    term P port IP end
    term GND end
    term VCC end
  end
  gate CLK2HWCLK cell HWCLOCK
    term P port IP end
    term Q port IC end
    term VCC end
    term GND end
  end
end
logical example_4bit_load
  gates 21
  nets 76
  gate I1.I3.I2 master SUPER_LOGIC end
  gate I1.I4.I2 master SUPER_LOGIC end
  gate I2.I3.I2 master SUPER_LOGIC end
  gate I2.I4.I2 master SUPER_LOGIC end
  gate I3.I2 master SUPER_LOGIC end
  gate I4.I1 master OUTPAD_25UM end
  gate I4.I2 master OUTPAD_25UM end
  gate I4.I3 master OUTPAD_25UM end
  gate I4.I4 master OUTPAD_25UM end
  gate I5.I1 master INPAD_25UM end
  gate I5.I2 master INPAD_25UM end
  gate I5.I3 master INPAD_25UM end
  gate I5.I4 master INPAD_25UM end
  gate I6 master INPAD_25UM end
  gate I7 master INPAD_25UM end
  gate I8 master CKPAD_25UM end
  gate I9 master CLK2HWCLK end
  gate I12.I3 master SUPER_LOGIC end
  gate I12.I16 master SUPER_LOGIC end
  gate I12.I17 master SUPER_LOGIC end
  gate I12.I18 master SUPER_LOGIC end
  net clk clock 1
    gate I12.I3 term DCLK end
    gate I12.I18 term DCLK end
    gate I12.I16 term DCLK end
    gate I12.I17 term DCLK end
    gate I3.I2 term DCLK end
    gate I2.I3.I2 term DCLK end
    gate I2.I4.I2 term DCLK end
    gate I1.I3.I2 term DCLK end
    gate I1.I4.I2 term DCLK end
    gate I9 term Q end
  end
  net clear clock 3
    gate I8 term Q end
    gate I12.I17 term QR end
    gate I12.I16 term QR end
    gate I12.I18 term QR end
    gate I12.I3 term QR end
  end
  net enable
    gate I7 term Q end
    gate I3.I2 term E1 end
  end
  net load
    gate I6 term Q end
    gate I3.I2 term PS end
  end
  net data_in[3]
    gate I5.I1 term Q end
    gate I1.I3.I2 term PS end
  end
  net data_in[2]
    gate I5.I2 term Q end
    gate I1.I3.I2 term E1 end
  end
  net data_in[1]
    gate I5.I3 term Q end
    gate I1.I4.I2 term PS end
  end
  net data_in[0]
    gate I5.I4 term Q end
    gate I1.I4.I2 term E1 end
  end
  net count[3]
    gate I12.I16 term Q2Z end
    gate I2.I3.I2 term PS end
  end
  net count[2]
    gate I12.I17 term Q2Z end
    gate I2.I3.I2 term E1 end
  end
  net count[1]
    gate I12.I18 term Q2Z end
    gate I2.I4.I2 term PS end
  end
  net count[0]
    gate I12.I18 term F1 end
    gate I12.I3 term E2 end
    gate I12.I3 term D1 end
    gate I12.I3 term Q2Z end
    gate I2.I4.I2 term E1 end
  end
  net enable_reg
    gate I12.I18 term A1 end
    gate I3.I2 term QZ end
  end
  net load_reg
    gate I12.I3 term A2 end
    gate I3.I2 term Q2Z end
  end
  net data_in_reg[3]
    gate I12.I16 term B1 end
    gate I1.I3.I2 term Q2Z end
  end
  net data_in_reg[2]
    gate I12.I17 term B1 end
    gate I1.I3.I2 term QZ end
  end
  net data_in_reg[1]
    gate I12.I18 term B1 end
    gate I1.I4.I2 term Q2Z end
  end
  net data_in_reg[0]
    gate I12.I3 term B1 end
    gate I1.I4.I2 term QZ end
  end
  net count_reg[3]
    gate I4.I4 term A end
    gate I2.I3.I2 term Q2Z end
  end
  net count_reg[2]
    gate I4.I3 term A end
    gate I2.I3.I2 term QZ end
  end
  net count_reg[1]
    gate I4.I2 term A end
    gate I2.I4.I2 term Q2Z end
  end
  net count_reg[0]
    gate I4.I1 term A end
    gate I2.I4.I2 term QZ end
  end
  net count_out[3] direction OUTPUT
    gate I4.I4 term P end
  end
  net count_out[2] direction OUTPUT
    gate I4.I3 term P end
  end
  net count_out[1] direction OUTPUT
    gate I4.I2 term P end
  end
  net count_out[0] direction OUTPUT
    gate I4.I1 term P end
  end
  net clk_in direction INPUT
    gate I9 term P end
  end
  net clear_in direction INPUT
    gate I8 term P end
  end
  net enable_in direction INPUT
    gate I7 term P end
  end
  net load_in direction INPUT
    gate I6 term P end
  end
  net data[3] direction INPUT
    gate I5.I1 term P end
  end
  net data[2] direction INPUT
    gate I5.I2 term P end
  end
  net data[1] direction INPUT
    gate I5.I3 term P end
  end
  net data[0] direction INPUT
    gate I5.I4 term P end
  end
  net .I1.I3.I2-AZ
    gate I1.I3.I2 term AZ end
  end
  net .I1.I3.I2-OZ
    gate I1.I3.I2 term OZ end
  end
  net .I1.I3.I2-NZ
    gate I1.I3.I2 term NZ end
  end
  net .I1.I3.I2-FZ
    gate I1.I3.I2 term FZ end
  end
  net .I1.I4.I2-AZ
    gate I1.I4.I2 term AZ end
  end
  net .I1.I4.I2-OZ
    gate I1.I4.I2 term OZ end
  end
  net .I1.I4.I2-NZ
    gate I1.I4.I2 term NZ end
  end
  net .I1.I4.I2-FZ
    gate I1.I4.I2 term FZ end
  end
  net .I2.I3.I2-AZ
    gate I2.I3.I2 term AZ end
  end
  net .I2.I3.I2-OZ
    gate I2.I3.I2 term OZ end
  end
  net .I2.I3.I2-NZ
    gate I2.I3.I2 term NZ end
  end
  net .I2.I3.I2-FZ
    gate I2.I3.I2 term FZ end
  end
  net .I2.I4.I2-AZ
    gate I2.I4.I2 term AZ end
  end
  net .I2.I4.I2-OZ
    gate I2.I4.I2 term OZ end
  end
  net .I2.I4.I2-NZ
    gate I2.I4.I2 term NZ end
  end
  net .I2.I4.I2-FZ
    gate I2.I4.I2 term FZ end
  end
  net .I3.I2-AZ
    gate I3.I2 term AZ end
  end
  net .I3.I2-OZ
    gate I3.I2 term OZ end
  end
  net .I3.I2-NZ
    gate I3.I2 term NZ end
  end
  net .I3.I2-FZ
    gate I3.I2 term FZ end
  end
  net .I12-load_N
    gate I12.I17 term OS end
    gate I12.I16 term OS end
    gate I12.I18 term OS end
    gate I12.I3 term AZ end
  end
  net .I12-Qd_a
    gate I12.I3 term PS end
    gate I12.I3 term OZ end
  end
  net .I12-Qd_r
    gate I12.I17 term F3 end
    gate I12.I16 term F5 end
    gate I12.I3 term QZ end
  end
  net .I12-enable_buf
    gate I12.I17 term NP end
    gate I12.I16 term NP end
    gate I12.I18 term NP end
    gate I12.I3 term NP end
    gate I12.I18 term AZ end
  end
  net .I12-Qc_r
    gate I12.I18 term QZ end
    gate I12.I18 term D1 end
    gate I12.I18 term E2 end
    gate I12.I16 term F3 end
    gate I12.I17 term F1 end
  end
  net .I12-Qc_a
    gate I12.I18 term PS end
    gate I12.I18 term OZ end
  end
  net .I12-Qa_a
    gate I12.I16 term PS end
    gate I12.I16 term OZ end
  end
  net .I12-Qb_a
    gate I12.I17 term PS end
    gate I12.I17 term OZ end
  end
  net .I12-Qa_r
    gate I12.I16 term E2 end
    gate I12.I16 term D1 end
    gate I12.I16 term QZ end
  end
  net .I12-Qb_r
    gate I12.I16 term F1 end
    gate I12.I17 term E2 end
    gate I12.I17 term D1 end
    gate I12.I17 term QZ end
  end
  net .I12.I3-NZ
    gate I12.I3 term NZ end
  end
  net .I12.I3-FZ
    gate I12.I3 term FZ end
  end
  net .I12.I16-AZ
    gate I12.I16 term AZ end
  end
  net .I12.I16-NZ
    gate I12.I16 term NZ end
  end
  net .I12.I16-FZ
    gate I12.I16 term FZ end
  end
  net .I12.I17-AZ
    gate I12.I17 term AZ end
  end
  net .I12.I17-NZ
    gate I12.I17 term NZ end
  end
  net .I12.I17-FZ
    gate I12.I17 term FZ end
  end
  net .I12.I18-NZ
    gate I12.I18 term NZ end
  end
  net .I12.I18-FZ
    gate I12.I18 term FZ end
  end
  net GND
    gate I1.I3.I2 term CLKSEL end
    gate I1.I3.I2 term A2 end
    gate I1.I3.I2 term A4 end
    gate I1.I3.I2 term A6 end
    gate I1.I3.I2 term B2 end
    gate I1.I3.I2 term C2 end
    gate I1.I3.I2 term D2 end
    gate I1.I3.I2 term E2 end
    gate I1.I3.I2 term F2 end