example_32bit_load.chp

VHDL examples for counter design, use QuickLogic eclips

  end
  net count_reg[15]
    gate outpad_25um[15] term A end
    gate I2.I6.I2 term Q2Z end
  end
  net count_reg[14]
    gate outpad_25um[14] term A end
    gate I2.I6.I2 term QZ end
  end
  net count_reg[13]
    gate outpad_25um[13] term A end
    gate I2.I7.I2 term Q2Z end
  end
  net count_reg[12]
    gate outpad_25um[12] term A end
    gate I2.I7.I2 term QZ end
  end
  net count_reg[11]
    gate outpad_25um[11] term A end
    gate I2.I8.I2 term Q2Z end
  end
  net count_reg[10]
    gate outpad_25um[10] term A end
    gate I2.I8.I2 term QZ end
  end
  net count_reg[9]
    gate outpad_25um[9] term A end
    gate I2.I9.I2 term Q2Z end
  end
  net count_reg[8]
    gate outpad_25um[8] term A end
    gate I2.I9.I2 term QZ end
  end
  net count_reg[7]
    gate outpad_25um[7] term A end
    gate I2.I2.I2 term Q2Z end
  end
  net count_reg[6]
    gate outpad_25um[6] term A end
    gate I2.I2.I2 term QZ end
  end
  net count_reg[5]
    gate outpad_25um[5] term A end
    gate I2.I3.I2 term Q2Z end
  end
  net count_reg[4]
    gate outpad_25um[4] term A end
    gate I2.I3.I2 term QZ end
  end
  net count_reg[3]
    gate outpad_25um[3] term A end
    gate I2.I4.I2 term Q2Z end
  end
  net count_reg[2]
    gate outpad_25um[2] term A end
    gate I2.I4.I2 term QZ end
  end
  net count_reg[1]
    gate outpad_25um[1] term A end
    gate I2.I5.I2 term Q2Z end
  end
  net count_reg[0]
    gate outpad_25um[0] term A end
    gate I2.I5.I2 term QZ end
  end
  net enable_reg
    gate I17.I9.I8.I11.I19 term F1 end
    gate I17.I9.I8.I10.I18 term D1 end
    gate I17.I9.I9.I16 term A1 end
    gate I17.I8.I16 term A1 end
    gate I3.I2 term QZ end
  end
  net load_reg
    gate I17.I9.I8.I11.I23 term F1 end
    gate I17.I9.I8.I11.I23 term A1 end
    gate I17.I9.I8.I10.I18 term A5 end
    gate I17.I9.I8.I10.I18 term F1 end
    gate I17.I9.I9.I15 term F1 end
    gate I17.I9.I9.I12 term F1 end
    gate I17.I8.I19.I3 term A2 end
    gate I17.I8.I18.I3 term A2 end
    gate I3.I2 term Q2Z end
  end
  net clk_in direction INPUT
    gate I9 term P end
  end
  net clear_in direction INPUT
    gate I8 term P end
  end
  net enable_in direction INPUT
    gate I7 term P end
  end
  net load_in direction INPUT
    gate I6 term P end
  end
  net data_reg[15]
    gate I17.I9.I8.I10.I20.I16 term B1 end
    gate I1.I6.I2 term Q2Z end
  end
  net data_reg[14]
    gate I17.I9.I8.I10.I20.I17 term B1 end
    gate I1.I6.I2 term QZ end
  end
  net data_reg[13]
    gate I17.I9.I8.I10.I20.I18 term B1 end
    gate I1.I7.I2 term Q2Z end
  end
  net data_reg[12]
    gate I17.I9.I8.I10.I20.I3 term B1 end
    gate I1.I7.I2 term QZ end
  end
  net data_reg[11]
    gate I17.I9.I8.I10.I19.I16 term B1 end
    gate I1.I8.I2 term Q2Z end
  end
  net data_reg[10]
    gate I17.I9.I8.I10.I19.I17 term B1 end
    gate I1.I8.I2 term QZ end
  end
  net data_reg[9]
    gate I17.I9.I8.I10.I19.I18 term B1 end
    gate I1.I9.I2 term Q2Z end
  end
  net data_reg[8]
    gate I17.I9.I8.I10.I19.I3 term B1 end
    gate I1.I9.I2 term QZ end
  end
  net data_reg[7]
    gate I17.I9.I8.I11.I24.I16 term B1 end
    gate I1.I2.I2 term Q2Z end
  end
  net data_reg[6]
    gate I17.I9.I8.I11.I24.I17 term B1 end
    gate I1.I2.I2 term QZ end
  end
  net data_reg[5]
    gate I17.I9.I8.I11.I24.I18 term B1 end
    gate I1.I3.I2 term Q2Z end
  end
  net data_reg[4]
    gate I17.I9.I8.I11.I24.I3 term B1 end
    gate I1.I3.I2 term QZ end
  end
  net data_reg[3]
    gate I17.I9.I8.I11.I25.I16 term B1 end
    gate I1.I4.I2 term Q2Z end
  end
  net data_reg[2]
    gate I17.I9.I8.I11.I25.I17 term B1 end
    gate I1.I4.I2 term QZ end
  end
  net data_reg[1]
    gate I17.I9.I8.I11.I25.I18 term B1 end
    gate I1.I5.I2 term Q2Z end
  end
  net data_reg[0]
    gate I17.I9.I8.I11.I25.I3 term B1 end
    gate I1.I5.I2 term QZ end
  end
  net count_reg[23]
    gate outpad_25um[23] term A end
    gate I16.I2.I2 term Q2Z end
  end
  net count_reg[22]
    gate outpad_25um[22] term A end
    gate I16.I2.I2 term QZ end
  end
  net count_reg[21]
    gate outpad_25um[21] term A end
    gate I16.I3.I2 term Q2Z end
  end
  net count_reg[20]
    gate outpad_25um[20] term A end
    gate I16.I3.I2 term QZ end
  end
  net count_reg[19]
    gate outpad_25um[19] term A end
    gate I16.I4.I2 term Q2Z end
  end
  net count_reg[18]
    gate outpad_25um[18] term A end
    gate I16.I4.I2 term QZ end
  end
  net count_reg[17]
    gate outpad_25um[17] term A end
    gate I16.I5.I2 term Q2Z end
  end
  net count_reg[16]
    gate outpad_25um[16] term A end
    gate I16.I5.I2 term QZ end
  end
  net data_in[23]
    gate I15.I2.I2 term PS end
    gate inpad_25um[23] term Q end
  end
  net data_in[22]
    gate I15.I2.I2 term E1 end
    gate inpad_25um[22] term Q end
  end
  net data_in[21]
    gate I15.I3.I2 term PS end
    gate inpad_25um[21] term Q end
  end
  net data_in[20]
    gate I15.I3.I2 term E1 end
    gate inpad_25um[20] term Q end
  end
  net data_in[19]
    gate I15.I4.I2 term PS end
    gate inpad_25um[19] term Q end
  end
  net data_in[18]
    gate I15.I4.I2 term E1 end
    gate inpad_25um[18] term Q end
  end
  net data_in[17]
    gate I15.I5.I2 term PS end
    gate inpad_25um[17] term Q end
  end
  net data_in[16]
    gate I15.I5.I2 term E1 end
    gate inpad_25um[16] term Q end
  end
  net data_in[15]
    gate inpad_25um[15] term Q end
    gate I1.I6.I2 term PS end
  end
  net data_in[14]
    gate inpad_25um[14] term Q end
    gate I1.I6.I2 term E1 end
  end
  net data_in[13]
    gate inpad_25um[13] term Q end
    gate I1.I7.I2 term PS end
  end
  net data_in[12]
    gate inpad_25um[12] term Q end
    gate I1.I7.I2 term E1 end
  end
  net data_in[11]
    gate inpad_25um[11] term Q end
    gate I1.I8.I2 term PS end
  end
  net data_in[10]
    gate inpad_25um[10] term Q end
    gate I1.I8.I2 term E1 end
  end
  net data_in[9]
    gate inpad_25um[9] term Q end
    gate I1.I9.I2 term PS end
  end
  net data_in[8]
    gate inpad_25um[8] term Q end
    gate I1.I9.I2 term E1 end
  end
  net data_in[7]
    gate inpad_25um[7] term Q end
    gate I1.I2.I2 term PS end
  end
  net data_in[6]
    gate inpad_25um[6] term Q end
    gate I1.I2.I2 term E1 end
  end
  net data_in[5]
    gate inpad_25um[5] term Q end
    gate I1.I3.I2 term PS end
  end
  net data_in[4]
    gate inpad_25um[4] term Q end
    gate I1.I3.I2 term E1 end
  end
  net data_in[3]
    gate inpad_25um[3] term Q end
    gate I1.I4.I2 term PS end
  end
  net data_in[2]
    gate inpad_25um[2] term Q end
    gate I1.I4.I2 term E1 end
  end
  net data_in[1]
    gate inpad_25um[1] term Q end
    gate I1.I5.I2 term PS end
  end
  net data_in[0]
    gate inpad_25um[0] term Q end
    gate I1.I5.I2 term E1 end
  end
  net data_reg[23]
    gate I17.I9.I9.I19.I16 term B1 end
    gate I15.I2.I2 term Q2Z end
  end
  net data_reg[22]
    gate I17.I9.I9.I19.I17 term B1 end
    gate I15.I2.I2 term QZ end
  end
  net data_reg[21]
    gate I17.I9.I9.I19.I18 term B1 end
    gate I15.I3.I2 term Q2Z end
  end
  net data_reg[20]
    gate I17.I9.I9.I19.I3 term B1 end
    gate I15.I3.I2 term QZ end
  end
  net data_reg[19]
    gate I17.I9.I9.I18.I16 term B1 end
    gate I15.I4.I2 term Q2Z end
  end
  net data_reg[18]
    gate I17.I9.I9.I18.I17 term B1 end
    gate I15.I4.I2 term QZ end
  end
  net data_reg[17]
    gate I17.I9.I9.I18.I18 term B1 end
    gate I15.I5.I2 term Q2Z end
  end
  net data_reg[16]
    gate I17.I9.I9.I18.I3 term B1 end
    gate I15.I5.I2 term QZ end
  end
  net count[23]
    gate I17.I9.I9.I19.I16 term Q2Z end
    gate I17.I9.I9.I12 term A1 end
    gate I16.I2.I2 term PS end
  end
  net count[22]
    gate I17.I9.I9.I19.I17 term Q2Z end
    gate I17.I9.I9.I12 term A3 end
    gate I16.I2.I2 term E1 end
  end
  net count[21]
    gate I17.I9.I9.I19.I18 term Q2Z end
    gate I17.I9.I9.I12 term A5 end
    gate I16.I3.I2 term PS end
  end
  net count[20]
    gate I17.I9.I9.I19.I18 term F1 end
    gate I17.I9.I9.I19.I3 term E2 end
    gate I17.I9.I9.I19.I3 term D1 end
    gate I17.I9.I9.I19.I3 term Q2Z end
    gate I17.I9.I9.I12 term D1 end
    gate I16.I3.I2 term E1 end
  end
  net count[19]
    gate I17.I9.I9.I18.I16 term Q2Z end
    gate I17.I9.I9.I15 term A1 end
    gate I16.I4.I2 term PS end
  end
  net count[18]
    gate I17.I9.I9.I18.I17 term Q2Z end
    gate I17.I9.I9.I15 term A3 end
    gate I16.I4.I2 term E1 end
  end
  net count[17]
    gate I17.I9.I9.I18.I18 term Q2Z end
    gate I17.I9.I9.I15 term A5 end
    gate I16.I5.I2 term PS end
  end
  net count[16]
    gate I17.I9.I9.I18.I18 term F1 end
    gate I17.I9.I9.I18.I3 term E2 end
    gate I17.I9.I9.I18.I3 term D1 end
    gate I17.I9.I9.I18.I3 term Q2Z end
    gate I17.I9.I9.I15 term D1 end
    gate I16.I5.I2 term E1 end
  end
  net data_in[31]
    gate I15.I6.I2 term PS end
    gate inpad_25um[31] term Q end
  end
  net data_in[30]
    gate I15.I6.I2 term E1 end
    gate inpad_25um[30] term Q end
  end
  net data_in[29]
    gate I15.I7.I2 term PS end
    gate inpad_25um[29] term Q end
  end
  net data_in[28]
    gate I15.I7.I2 term E1 end
    gate inpad_25um[28] term Q end
  end
  net data_in[27]
    gate I15.I8.I2 term PS end
    gate inpad_25um[27] term Q end
  end
  net data_in[26]
    gate I15.I8.I2 term E1 end
    gate inpad_25um[26] term Q end
  end
  net data_in[25]
    gate I15.I9.I2 term PS end
    gate inpad_25um[25] term Q end
  end
  net data_in[24]
    gate I15.I9.I2 term E1 end
    gate inpad_25um[24] term Q end
  end
  net data_reg[31]
    gate I17.I8.I19.I16 term B1 end
    gate I15.I6.I2 term Q2Z end
  end
  net data_reg[30]
    gate I17.I8.I19.I17 term B1 end
    gate I15.I6.I2 term QZ end
  end
  net data_reg[29]
    gate I17.I8.I19.I18 term B1 end
    gate I15.I7.I2 term Q2Z end
  end
  net data_reg[28]
    gate I17.I8.I19.I3 term B1 end
    gate I15.I7.I2 term QZ end
  end
  net data_reg[27]
    gate I17.I8.I18.I16 term B1 end
    gate I15.I8.I2 term Q2Z end
  end
  net data_reg[26]
    gate I17.I8.I18.I17 term B1 end
    gate I15.I8.I2 term QZ end
  end
  net data_reg[25]
    gate I17.I8.I18.I18 term B1 end
    gate I15.I9.I2 term Q2Z end
  end
  net data_reg[24]
    gate I17.I8.I18.I3 term B1 end
    gate I15.I9.I2 term QZ end
  end
  net count[31]
    gate I17.I8.I19.I16 term Q2Z end
    gate I16.I6.I2 term PS end
  end
  net count[30]
    gate I17.I8.I19.I17 term Q2Z end
    gate I16.I6.I2 term E1 end
  end
  net count[29]
    gate I17.I8.I19.I18 term Q2Z end
    gate I16.I7.I2 term PS end
  end
  net count[28]
    gate I17.I8.I19.I18 term F1 end
    gate I17.I8.I19.I3 term E2 end
    gate I17.I8.I19.I3 term D1 end
    gate I17.I8.I19.I3 term Q2Z end
    gate I16.I7.I2 term E1 end
  end
  net count[27]
    gate I17.I8.I18.I16 term Q2Z end
    gate I17.I8.I15 term A1 end
    gate I16.I8.I2 term PS end
  end
  net count[26]
    gate I17.I8.I18.I17 term Q2Z end
    gate I17.I8.I15 term A3 end
    gate I16.I8.I2 term E1 end
  end
  net count[25]
    gate I17.I8.I18.I18 term Q2Z end
    gate I17.I8.I15 term A5 end
    gate I16.I9.I2 term PS end
  end
  net count[24]
    gate I17.I8.I18.I18 term F1 end
    gate I17.I8.I18.I3 term E2 end
    gate I17.I8.I18.I3 term D1 end
    gate I17.I8.I18.I3 term Q2Z end
    gate I17.I8.I15 term D1 end
    gate I16.I9.I2 term E1 end
  end
  net count_reg[31]