📄 example_32bit_load.chp
字号:
term SIGN2 port SIGN2 end
term SIGN1 port SIGN1 end
term RESET port RESET end
term CLK port CLK end
term A[15] port A15 end
term A[14] port A14 end
term A[13] port A13 end
term A[12] port A12 end
term A[11] port A11 end
term A[10] port A10 end
term A[9] port A9 end
term A[8] port A8 end
term A[7] port A7 end
term A[6] port A6 end
term A[5] port A5 end
term A[4] port A4 end
term A[3] port A3 end
term A[2] port A2 end
term A[1] port A1 end
term A[0] port A0 end
term B[15] port B15 end
term B[14] port B14 end
term B[13] port B13 end
term B[12] port B12 end
term B[11] port B11 end
term B[10] port B10 end
term B[9] port B9 end
term B[8] port B8 end
term B[7] port B7 end
term B[6] port B6 end
term B[5] port B5 end
term B[4] port B4 end
term B[3] port B3 end
term B[2] port B2 end
term B[1] port B1 end
term B[0] port B0 end
term S3 port S3 end
term S2 port S2 end
term S1 port S1 end
term CIN port CIN end
term Q[16] port OUT16 end
term Q[15] port OUT15 end
term Q[14] port OUT14 end
term Q[13] port OUT13 end
term Q[12] port OUT12 end
term Q[11] port OUT11 end
term Q[10] port OUT10 end
term Q[9] port OUT9 end
term Q[8] port OUT8 end
term Q[7] port OUT7 end
term Q[6] port OUT6 end
term Q[5] port OUT5 end
term Q[4] port OUT4 end
term Q[3] port OUT3 end
term Q[2] port OUT2 end
term Q[1] port OUT1 end
term Q[0] port OUT0 end
term GND end
term VCC end
end
gate PLL_TOP cell PLL
term S4 port S4 end
term S3 port S3 end
term S2 port S2 end
term S1 port S1 end
term LOCK_DETECTn port LD end
term PLLCLK_NET port PLLCK end
term CLKPAD_OUT port PLLOUT end
term PLL_RESET port PLLRST end
term PLLCLK_IN port PLLIN end
term GND end
term VCC end
end
gate PLL_OUTPAD_25UM cell PLLOUTPAD
term S port SEL end
term P port IP end
term A port IZ end
term GND end
term VCC end
end
gate PLL_RSTPAD_25UM cell PLLRSTPAD
term Q port IZ end
term P port IP end
term GND end
term VCC end
end
gate PLL_CLKPAD_25UM cell CLOCK
term O port OP end
term Q port IC end
term P port IP end
term GND end
term VCC end
end
gate CLK2HWCLK cell HWCLOCK
term P port IP end
term Q port IC end
term VCC end
term GND end
end
end
logical example_32bit_load
gates 144
nets 565
gate I1.I2.I2 master SUPER_LOGIC end
gate I1.I3.I2 master SUPER_LOGIC end
gate I1.I4.I2 master SUPER_LOGIC end
gate I1.I5.I2 master SUPER_LOGIC end
gate I1.I6.I2 master SUPER_LOGIC end
gate I1.I7.I2 master SUPER_LOGIC end
gate I1.I8.I2 master SUPER_LOGIC end
gate I1.I9.I2 master SUPER_LOGIC end
gate I2.I2.I2 master SUPER_LOGIC end
gate I2.I3.I2 master SUPER_LOGIC end
gate I2.I4.I2 master SUPER_LOGIC end
gate I2.I5.I2 master SUPER_LOGIC end
gate I2.I6.I2 master SUPER_LOGIC end
gate I2.I7.I2 master SUPER_LOGIC end
gate I2.I8.I2 master SUPER_LOGIC end
gate I2.I9.I2 master SUPER_LOGIC end
gate I3.I2 master SUPER_LOGIC end
gate I6 master INPAD_25UM end
gate I7 master INPAD_25UM end
gate I8 master CKPAD_25UM end
gate I9 master CLK2HWCLK end
gate I15.I2.I2 master SUPER_LOGIC end
gate I15.I3.I2 master SUPER_LOGIC end
gate I15.I4.I2 master SUPER_LOGIC end
gate I15.I5.I2 master SUPER_LOGIC end
gate I15.I6.I2 master SUPER_LOGIC end
gate I15.I7.I2 master SUPER_LOGIC end
gate I15.I8.I2 master SUPER_LOGIC end
gate I15.I9.I2 master SUPER_LOGIC end
gate I16.I2.I2 master SUPER_LOGIC end
gate I16.I3.I2 master SUPER_LOGIC end
gate I16.I4.I2 master SUPER_LOGIC end
gate I16.I5.I2 master SUPER_LOGIC end
gate I16.I6.I2 master SUPER_LOGIC end
gate I16.I7.I2 master SUPER_LOGIC end
gate I16.I8.I2 master SUPER_LOGIC end
gate I16.I9.I2 master SUPER_LOGIC end
gate I17.I8.I15 master SUPER_LOGIC pack end
gate I17.I8.I16 master SUPER_LOGIC pack end
gate I17.I8.I18.I3 master SUPER_LOGIC end
gate I17.I8.I18.I16 master SUPER_LOGIC end
gate I17.I8.I18.I17 master SUPER_LOGIC end
gate I17.I8.I18.I18 master SUPER_LOGIC end
gate I17.I8.I19.I3 master SUPER_LOGIC end
gate I17.I8.I19.I16 master SUPER_LOGIC end
gate I17.I8.I19.I17 master SUPER_LOGIC end
gate I17.I8.I19.I18 master SUPER_LOGIC end
gate I17.I9.I8.I10.I12 master SUPER_LOGIC pack end
gate I17.I9.I8.I10.I15 master SUPER_LOGIC pack end
gate I17.I9.I8.I10.I18 master SUPER_LOGIC pack end
gate I17.I9.I8.I10.I19.I3 master SUPER_LOGIC end
gate I17.I9.I8.I10.I19.I16 master SUPER_LOGIC end
gate I17.I9.I8.I10.I19.I17 master SUPER_LOGIC end
gate I17.I9.I8.I10.I19.I18 master SUPER_LOGIC end
gate I17.I9.I8.I10.I20.I3 master SUPER_LOGIC end
gate I17.I9.I8.I10.I20.I16 master SUPER_LOGIC end
gate I17.I9.I8.I10.I20.I17 master SUPER_LOGIC end
gate I17.I9.I8.I10.I20.I18 master SUPER_LOGIC end
gate I17.I9.I8.I11.I14 master SUPER_LOGIC pack end
gate I17.I9.I8.I11.I19 master SUPER_LOGIC pack end
gate I17.I9.I8.I11.I23 master SUPER_LOGIC pack end
gate I17.I9.I8.I11.I24.I3 master SUPER_LOGIC end
gate I17.I9.I8.I11.I24.I16 master SUPER_LOGIC end
gate I17.I9.I8.I11.I24.I17 master SUPER_LOGIC end
gate I17.I9.I8.I11.I24.I18 master SUPER_LOGIC end
gate I17.I9.I8.I11.I25.I3 master SUPER_LOGIC end
gate I17.I9.I8.I11.I25.I16 master SUPER_LOGIC end
gate I17.I9.I8.I11.I25.I17 master SUPER_LOGIC end
gate I17.I9.I8.I11.I25.I18 master SUPER_LOGIC end
gate I17.I9.I9.I12 master SUPER_LOGIC pack end
gate I17.I9.I9.I15 master SUPER_LOGIC pack end
gate I17.I9.I9.I16 master SUPER_LOGIC pack end
gate I17.I9.I9.I18.I3 master SUPER_LOGIC end
gate I17.I9.I9.I18.I16 master SUPER_LOGIC end
gate I17.I9.I9.I18.I17 master SUPER_LOGIC end
gate I17.I9.I9.I18.I18 master SUPER_LOGIC end
gate I17.I9.I9.I19.I3 master SUPER_LOGIC end
gate I17.I9.I9.I19.I16 master SUPER_LOGIC end
gate I17.I9.I9.I19.I17 master SUPER_LOGIC end
gate I17.I9.I9.I19.I18 master SUPER_LOGIC end
gate inpad_25um[31] master INPAD_25UM end
gate inpad_25um[30] master INPAD_25UM end
gate inpad_25um[29] master INPAD_25UM end
gate inpad_25um[28] master INPAD_25UM end
gate inpad_25um[27] master INPAD_25UM end
gate inpad_25um[26] master INPAD_25UM end
gate inpad_25um[25] master INPAD_25UM end
gate inpad_25um[24] master INPAD_25UM end
gate inpad_25um[23] master INPAD_25UM end
gate inpad_25um[22] master INPAD_25UM end
gate inpad_25um[21] master INPAD_25UM end
gate inpad_25um[20] master INPAD_25UM end
gate inpad_25um[19] master INPAD_25UM end
gate inpad_25um[18] master INPAD_25UM end
gate inpad_25um[17] master INPAD_25UM end
gate inpad_25um[16] master INPAD_25UM end
gate inpad_25um[15] master INPAD_25UM end
gate inpad_25um[14] master INPAD_25UM end
gate inpad_25um[13] master INPAD_25UM end
gate inpad_25um[12] master INPAD_25UM end
gate inpad_25um[11] master INPAD_25UM end
gate inpad_25um[10] master INPAD_25UM end
gate inpad_25um[9] master INPAD_25UM end
gate inpad_25um[8] master INPAD_25UM end
gate inpad_25um[7] master INPAD_25UM end
gate inpad_25um[6] master INPAD_25UM end
gate inpad_25um[5] master INPAD_25UM end
gate inpad_25um[4] master INPAD_25UM end
gate inpad_25um[3] master INPAD_25UM end
gate inpad_25um[2] master INPAD_25UM end
gate inpad_25um[1] master INPAD_25UM end
gate inpad_25um[0] master INPAD_25UM end
gate outpad_25um[31] master OUTPAD_25UM end
gate outpad_25um[30] master OUTPAD_25UM end
gate outpad_25um[29] master OUTPAD_25UM end
gate outpad_25um[28] master OUTPAD_25UM end
gate outpad_25um[27] master OUTPAD_25UM end
gate outpad_25um[26] master OUTPAD_25UM end
gate outpad_25um[25] master OUTPAD_25UM end
gate outpad_25um[24] master OUTPAD_25UM end
gate outpad_25um[23] master OUTPAD_25UM end
gate outpad_25um[22] master OUTPAD_25UM end
gate outpad_25um[21] master OUTPAD_25UM end
gate outpad_25um[20] master OUTPAD_25UM end
gate outpad_25um[19] master OUTPAD_25UM end
gate outpad_25um[18] master OUTPAD_25UM end
gate outpad_25um[17] master OUTPAD_25UM end
gate outpad_25um[16] master OUTPAD_25UM end
gate outpad_25um[15] master OUTPAD_25UM end
gate outpad_25um[14] master OUTPAD_25UM end
gate outpad_25um[13] master OUTPAD_25UM end
gate outpad_25um[12] master OUTPAD_25UM end
gate outpad_25um[11] master OUTPAD_25UM end
gate outpad_25um[10] master OUTPAD_25UM end
gate outpad_25um[9] master OUTPAD_25UM end
gate outpad_25um[8] master OUTPAD_25UM end
gate outpad_25um[7] master OUTPAD_25UM end
gate outpad_25um[6] master OUTPAD_25UM end
gate outpad_25um[5] master OUTPAD_25UM end
gate outpad_25um[4] master OUTPAD_25UM end
gate outpad_25um[3] master OUTPAD_25UM end
gate outpad_25um[2] master OUTPAD_25UM end
gate outpad_25um[1] master OUTPAD_25UM end
gate outpad_25um[0] master OUTPAD_25UM end
net clk clock 1
gate I1.I9.I2 term DCLK end
gate I1.I8.I2 term DCLK end
gate I1.I7.I2 term DCLK end
gate I1.I6.I2 term DCLK end
gate I1.I5.I2 term DCLK end
gate I1.I4.I2 term DCLK end
gate I1.I3.I2 term DCLK end
gate I1.I2.I2 term DCLK end
gate I15.I9.I2 term DCLK end
gate I15.I8.I2 term DCLK end
gate I15.I7.I2 term DCLK end
gate I15.I6.I2 term DCLK end
gate I15.I5.I2 term DCLK end
gate I15.I4.I2 term DCLK end
gate I15.I3.I2 term DCLK end
gate I15.I2.I2 term DCLK end
gate I2.I9.I2 term DCLK end
gate I2.I8.I2 term DCLK end
gate I2.I7.I2 term DCLK end
gate I2.I6.I2 term DCLK end
gate I2.I5.I2 term DCLK end
gate I2.I4.I2 term DCLK end
gate I2.I3.I2 term DCLK end
gate I2.I2.I2 term DCLK end
gate I16.I9.I2 term DCLK end
gate I16.I8.I2 term DCLK end
gate I16.I7.I2 term DCLK end
gate I16.I6.I2 term DCLK end
gate I16.I5.I2 term DCLK end
gate I16.I4.I2 term DCLK end
gate I16.I3.I2 term DCLK end
gate I16.I2.I2 term DCLK end
gate I3.I2 term DCLK end
gate I17.I8.I15 term DCLK end
gate I17.I8.I16 term DCLK end
gate I17.I8.I19.I3 term DCLK end
gate I17.I8.I19.I18 term DCLK end
gate I17.I8.I19.I16 term DCLK end
gate I17.I8.I19.I17 term DCLK end
gate I17.I8.I18.I3 term DCLK end
gate I17.I8.I18.I18 term DCLK end
gate I17.I8.I18.I16 term DCLK end
gate I17.I8.I18.I17 term DCLK end
gate I17.I9.I9.I15 term DCLK end
gate I17.I9.I9.I16 term DCLK end
gate I17.I9.I9.I12 term DCLK end
gate I17.I9.I9.I19.I3 term DCLK end
gate I17.I9.I9.I19.I18 term DCLK end
gate I17.I9.I9.I19.I16 term DCLK end
gate I17.I9.I9.I19.I17 term DCLK end
gate I17.I9.I9.I18.I3 term DCLK end
gate I17.I9.I9.I18.I18 term DCLK end
gate I17.I9.I9.I18.I16 term DCLK end
gate I17.I9.I9.I18.I17 term DCLK end
gate I17.I9.I8.I10.I19.I3 term DCLK end
gate I17.I9.I8.I10.I19.I18 term DCLK end
gate I17.I9.I8.I10.I19.I16 term DCLK end
gate I17.I9.I8.I10.I19.I17 term DCLK end
gate I17.I9.I8.I10.I20.I3 term DCLK end
gate I17.I9.I8.I10.I20.I18 term DCLK end
gate I17.I9.I8.I10.I20.I16 term DCLK end
gate I17.I9.I8.I10.I20.I17 term DCLK end
gate I17.I9.I8.I10.I15 term DCLK end
gate I17.I9.I8.I10.I12 term DCLK end
gate I17.I9.I8.I10.I18 term DCLK end
gate I17.I9.I8.I11.I24.I3 term DCLK end
gate I17.I9.I8.I11.I24.I18 term DCLK end
gate I17.I9.I8.I11.I24.I16 term DCLK end
gate I17.I9.I8.I11.I24.I17 term DCLK end
gate I17.I9.I8.I11.I25.I3 term DCLK end
gate I17.I9.I8.I11.I25.I18 term DCLK end
gate I17.I9.I8.I11.I25.I16 term DCLK end
gate I17.I9.I8.I11.I25.I17 term DCLK end
gate I17.I9.I8.I11.I19 term DCLK end
gate I17.I9.I8.I11.I14 term DCLK end
gate I17.I9.I8.I11.I23 term DCLK end
gate I9 term Q end
end
net enable
gate I3.I2 term E1 end
gate I7 term Q end
end
net load
gate I3.I2 term PS end
gate I6 term Q end
end
net clear clock 3
gate I17.I9.I8.I11.I23 term QR end
gate I17.I9.I8.I11.I14 term QR end
gate I17.I9.I8.I11.I19 term QR end
gate I17.I9.I8.I11.I25.I17 term QR end
gate I17.I9.I8.I11.I25.I16 term QR end
gate I17.I9.I8.I11.I25.I18 term QR end
gate I17.I9.I8.I11.I25.I3 term QR end
gate I17.I9.I8.I11.I24.I17 term QR end
gate I17.I9.I8.I11.I24.I16 term QR end
gate I17.I9.I8.I11.I24.I18 term QR end
gate I17.I9.I8.I11.I24.I3 term QR end
gate I17.I9.I8.I10.I18 term QR end
gate I17.I9.I8.I10.I12 term QR end
gate I17.I9.I8.I10.I15 term QR end
gate I17.I9.I8.I10.I20.I17 term QR end
gate I17.I9.I8.I10.I20.I16 term QR end
gate I17.I9.I8.I10.I20.I18 term QR end
gate I17.I9.I8.I10.I20.I3 term QR end
gate I17.I9.I8.I10.I19.I17 term QR end
gate I17.I9.I8.I10.I19.I16 term QR end
gate I17.I9.I8.I10.I19.I18 term QR end
gate I17.I9.I8.I10.I19.I3 term QR end
gate I17.I9.I9.I18.I17 term QR end
gate I17.I9.I9.I18.I16 term QR end
gate I17.I9.I9.I18.I18 term QR end
gate I17.I9.I9.I18.I3 term QR end
gate I17.I9.I9.I19.I17 term QR end
gate I17.I9.I9.I19.I16 term QR end
gate I17.I9.I9.I19.I18 term QR end
gate I17.I9.I9.I19.I3 term QR end
gate I17.I9.I9.I12 term QR end
gate I17.I9.I9.I16 term QR end
gate I17.I9.I9.I15 term QR end
gate I17.I8.I18.I17 term QR end
gate I17.I8.I18.I16 term QR end
gate I17.I8.I18.I18 term QR end
gate I17.I8.I18.I3 term QR end
gate I17.I8.I19.I17 term QR end
gate I17.I8.I19.I16 term QR end
gate I17.I8.I19.I18 term QR end
gate I17.I8.I19.I3 term QR end
gate I17.I8.I16 term QR end
gate I17.I8.I15 term QR end
gate I8 term Q end
end
net count[15]
gate I17.I9.I8.I10.I20.I16 term Q2Z end
gate I17.I9.I8.I10.I12 term A1 end
gate I2.I6.I2 term PS end
end
net count[14]
gate I17.I9.I8.I10.I20.I17 term Q2Z end
gate I17.I9.I8.I10.I12 term A3 end
gate I2.I6.I2 term E1 end
end
net count[13]
gate I17.I9.I8.I10.I20.I18 term Q2Z end
gate I17.I9.I8.I10.I12 term A5 end
gate I2.I7.I2 term PS end
end
net count[12]
gate I17.I9.I8.I10.I20.I18 term F1 end
gate I17.I9.I8.I10.I20.I3 term E2 end
gate I17.I9.I8.I10.I20.I3 term D1 end
gate I17.I9.I8.I10.I20.I3 term Q2Z end
gate I17.I9.I8.I10.I12 term D1 end
gate I2.I7.I2 term E1 end
end
net count[11]
gate I17.I9.I8.I10.I19.I16 term Q2Z end
gate I17.I9.I8.I10.I15 term A1 end
gate I2.I8.I2 term PS end
end
net count[10]
gate I17.I9.I8.I10.I19.I17 term Q2Z end
gate I17.I9.I8.I10.I15 term A3 end
gate I2.I8.I2 term E1 end
end
net count[9]
gate I17.I9.I8.I10.I19.I18 term Q2Z end
gate I17.I9.I8.I10.I15 term A5 end
gate I2.I9.I2 term PS end
end
net count[8]
gate I17.I9.I8.I10.I19.I18 term F1 end
gate I17.I9.I8.I10.I19.I3 term E2 end
gate I17.I9.I8.I10.I19.I3 term D1 end
gate I17.I9.I8.I10.I19.I3 term Q2Z end
gate I17.I9.I8.I10.I15 term D1 end
gate I2.I9.I2 term E1 end
end
net count[7]
gate I17.I9.I8.I11.I24.I16 term Q2Z end
gate I17.I9.I8.I11.I19 term A1 end
gate I2.I2.I2 term PS end
end
net count[6]
gate I17.I9.I8.I11.I24.I17 term Q2Z end
gate I17.I9.I8.I11.I19 term A3 end
gate I2.I2.I2 term E1 end
end
net count[5]
gate I17.I9.I8.I11.I24.I18 term Q2Z end
gate I17.I9.I8.I11.I19 term A5 end
gate I2.I3.I2 term PS end
end
net count[4]
gate I17.I9.I8.I11.I24.I18 term F1 end
gate I17.I9.I8.I11.I24.I3 term E2 end
gate I17.I9.I8.I11.I24.I3 term D1 end
gate I17.I9.I8.I11.I24.I3 term Q2Z end
gate I17.I9.I8.I11.I19 term D1 end
gate I2.I3.I2 term E1 end
end
net count[3]
gate I17.I9.I8.I11.I25.I16 term Q2Z end
gate I17.I9.I8.I11.I14 term A1 end
gate I2.I4.I2 term PS end
end
net count[2]
gate I17.I9.I8.I11.I25.I17 term Q2Z end
gate I17.I9.I8.I11.I14 term A3 end
gate I2.I4.I2 term E1 end
end
net count[1]
gate I17.I9.I8.I11.I25.I18 term Q2Z end
gate I17.I9.I8.I11.I14 term A5 end
gate I2.I5.I2 term PS end
end
net count[0]
gate I17.I9.I8.I11.I25.I18 term F1 end
gate I17.I9.I8.I11.I25.I3 term E2 end
gate I17.I9.I8.I11.I25.I3 term D1 end
gate I17.I9.I8.I11.I25.I3 term Q2Z end
gate I17.I9.I8.I11.I14 term D1 end
gate I17.I9.I8.I11.I14 term E2 end
gate I2.I5.I2 term E1 end
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