example_16bit_load.chp

VHDL examples for counter design, use QuickLogic eclips

  net count_reg[5]
    gate I2.I3.I2 term Q2Z end
    gate I4.I6 term A end
  end
  net count_reg[4]
    gate I2.I3.I2 term QZ end
    gate I4.I5 term A end
  end
  net count_reg[3]
    gate I2.I4.I2 term Q2Z end
    gate I4.I4 term A end
  end
  net count_reg[2]
    gate I2.I4.I2 term QZ end
    gate I4.I3 term A end
  end
  net count_reg[1]
    gate I2.I5.I2 term Q2Z end
    gate I4.I2 term A end
  end
  net count_reg[0]
    gate I2.I5.I2 term QZ end
    gate I4.I1 term A end
  end
  net enable_reg
    gate I12.I10.I18 term D1 end
    gate I12.I11.I19 term F1 end
    gate I3.I2 term QZ end
  end
  net load_reg
    gate I3.I2 term Q2Z end
  end
  net data[15] direction INPUT
    gate I5.I1 term P end
  end
  net data[14] direction INPUT
    gate I5.I2 term P end
  end
  net data[13] direction INPUT
    gate I5.I3 term P end
  end
  net data[12] direction INPUT
    gate I5.I4 term P end
  end
  net data[11] direction INPUT
    gate I5.I8 term P end
  end
  net data[10] direction INPUT
    gate I5.I7 term P end
  end
  net data[9] direction INPUT
    gate I5.I6 term P end
  end
  net data[8] direction INPUT
    gate I5.I5 term P end
  end
  net data[7] direction INPUT
    gate I5.I9 term P end
  end
  net data[6] direction INPUT
    gate I5.I10 term P end
  end
  net data[5] direction INPUT
    gate I5.I11 term P end
  end
  net data[4] direction INPUT
    gate I5.I12 term P end
  end
  net data[3] direction INPUT
    gate I5.I13 term P end
  end
  net data[2] direction INPUT
    gate I5.I14 term P end
  end
  net data[1] direction INPUT
    gate I5.I15 term P end
  end
  net data[0] direction INPUT
    gate I5.I16 term P end
  end
  net count_out[15] direction OUTPUT
    gate I4.I16 term P end
  end
  net count_out[14] direction OUTPUT
    gate I4.I15 term P end
  end
  net count_out[13] direction OUTPUT
    gate I4.I14 term P end
  end
  net count_out[12] direction OUTPUT
    gate I4.I13 term P end
  end
  net count_out[11] direction OUTPUT
    gate I4.I12 term P end
  end
  net count_out[10] direction OUTPUT
    gate I4.I11 term P end
  end
  net count_out[9] direction OUTPUT
    gate I4.I10 term P end
  end
  net count_out[8] direction OUTPUT
    gate I4.I9 term P end
  end
  net count_out[7] direction OUTPUT
    gate I4.I8 term P end
  end
  net count_out[6] direction OUTPUT
    gate I4.I7 term P end
  end
  net count_out[5] direction OUTPUT
    gate I4.I6 term P end
  end
  net count_out[4] direction OUTPUT
    gate I4.I5 term P end
  end
  net count_out[3] direction OUTPUT
    gate I4.I4 term P end
  end
  net count_out[2] direction OUTPUT
    gate I4.I3 term P end
  end
  net count_out[1] direction OUTPUT
    gate I4.I2 term P end
  end
  net count_out[0] direction OUTPUT
    gate I4.I1 term P end
  end
  net clk_in direction INPUT
    gate I9 term P end
  end
  net clear_in direction INPUT
    gate I8 term P end
  end
  net enable_in direction INPUT
    gate I7 term P end
  end
  net load_in direction INPUT
    gate I6 term P end
  end
  net data_reg[15]
    gate I12.I10.I20.I16 term B1 end
    gate I1.I6.I2 term Q2Z end
  end
  net data_reg[14]
    gate I12.I10.I20.I17 term B1 end
    gate I1.I6.I2 term QZ end
  end
  net data_reg[13]
    gate I12.I10.I20.I18 term B1 end
    gate I1.I7.I2 term Q2Z end
  end
  net data_reg[12]
    gate I12.I10.I20.I3 term B1 end
    gate I1.I7.I2 term QZ end
  end
  net data_reg[11]
    gate I12.I10.I19.I16 term B1 end
    gate I1.I8.I2 term Q2Z end
  end
  net data_reg[10]
    gate I12.I10.I19.I17 term B1 end
    gate I1.I8.I2 term QZ end
  end
  net data_reg[9]
    gate I12.I10.I19.I18 term B1 end
    gate I1.I9.I2 term Q2Z end
  end
  net data_reg[8]
    gate I12.I10.I19.I3 term B1 end
    gate I1.I9.I2 term QZ end
  end
  net data_reg[7]
    gate I12.I11.I24.I16 term B1 end
    gate I1.I2.I2 term Q2Z end
  end
  net data_reg[6]
    gate I12.I11.I24.I17 term B1 end
    gate I1.I2.I2 term QZ end
  end
  net data_reg[5]
    gate I12.I11.I24.I18 term B1 end
    gate I1.I3.I2 term Q2Z end
  end
  net data_reg[4]
    gate I12.I11.I24.I3 term B1 end
    gate I1.I3.I2 term QZ end
  end
  net data_reg[3]
    gate I12.I11.I25.I16 term B1 end
    gate I1.I4.I2 term Q2Z end
  end
  net data_reg[2]
    gate I12.I11.I25.I17 term B1 end
    gate I1.I4.I2 term QZ end
  end
  net data_reg[1]
    gate I12.I11.I25.I18 term B1 end
    gate I1.I5.I2 term Q2Z end
  end
  net data_reg[0]
    gate I12.I11.I25.I3 term B1 end
    gate I1.I5.I2 term QZ end
  end
  net .I1.I2.I2-AZ
    gate I1.I2.I2 term AZ end
  end
  net .I1.I2.I2-OZ
    gate I1.I2.I2 term OZ end
  end
  net .I1.I2.I2-NZ
    gate I1.I2.I2 term NZ end
  end
  net .I1.I2.I2-FZ
    gate I1.I2.I2 term FZ end
  end
  net .I1.I3.I2-AZ
    gate I1.I3.I2 term AZ end
  end
  net .I1.I3.I2-OZ
    gate I1.I3.I2 term OZ end
  end
  net .I1.I3.I2-NZ
    gate I1.I3.I2 term NZ end
  end
  net .I1.I3.I2-FZ
    gate I1.I3.I2 term FZ end
  end
  net .I1.I4.I2-AZ
    gate I1.I4.I2 term AZ end
  end
  net .I1.I4.I2-OZ
    gate I1.I4.I2 term OZ end
  end
  net .I1.I4.I2-NZ
    gate I1.I4.I2 term NZ end
  end
  net .I1.I4.I2-FZ
    gate I1.I4.I2 term FZ end
  end
  net .I1.I5.I2-AZ
    gate I1.I5.I2 term AZ end
  end
  net .I1.I5.I2-OZ
    gate I1.I5.I2 term OZ end
  end
  net .I1.I5.I2-NZ
    gate I1.I5.I2 term NZ end
  end
  net .I1.I5.I2-FZ
    gate I1.I5.I2 term FZ end
  end
  net .I1.I6.I2-AZ
    gate I1.I6.I2 term AZ end
  end
  net .I1.I6.I2-OZ
    gate I1.I6.I2 term OZ end
  end
  net .I1.I6.I2-NZ
    gate I1.I6.I2 term NZ end
  end
  net .I1.I6.I2-FZ
    gate I1.I6.I2 term FZ end
  end
  net .I1.I7.I2-AZ
    gate I1.I7.I2 term AZ end
  end
  net .I1.I7.I2-OZ
    gate I1.I7.I2 term OZ end
  end
  net .I1.I7.I2-NZ
    gate I1.I7.I2 term NZ end
  end
  net .I1.I7.I2-FZ
    gate I1.I7.I2 term FZ end
  end
  net .I1.I8.I2-AZ
    gate I1.I8.I2 term AZ end
  end
  net .I1.I8.I2-OZ
    gate I1.I8.I2 term OZ end
  end
  net .I1.I8.I2-NZ
    gate I1.I8.I2 term NZ end
  end
  net .I1.I8.I2-FZ
    gate I1.I8.I2 term FZ end
  end
  net .I1.I9.I2-AZ
    gate I1.I9.I2 term AZ end
  end
  net .I1.I9.I2-OZ
    gate I1.I9.I2 term OZ end
  end
  net .I1.I9.I2-NZ
    gate I1.I9.I2 term NZ end
  end
  net .I1.I9.I2-FZ
    gate I1.I9.I2 term FZ end
  end
  net .I2.I2.I2-AZ
    gate I2.I2.I2 term AZ end
  end
  net .I2.I2.I2-OZ
    gate I2.I2.I2 term OZ end
  end
  net .I2.I2.I2-NZ
    gate I2.I2.I2 term NZ end
  end
  net .I2.I2.I2-FZ
    gate I2.I2.I2 term FZ end
  end
  net .I2.I3.I2-AZ
    gate I2.I3.I2 term AZ end
  end
  net .I2.I3.I2-OZ
    gate I2.I3.I2 term OZ end
  end
  net .I2.I3.I2-NZ
    gate I2.I3.I2 term NZ end
  end
  net .I2.I3.I2-FZ
    gate I2.I3.I2 term FZ end
  end
  net .I2.I4.I2-AZ
    gate I2.I4.I2 term AZ end
  end
  net .I2.I4.I2-OZ
    gate I2.I4.I2 term OZ end
  end
  net .I2.I4.I2-NZ
    gate I2.I4.I2 term NZ end
  end
  net .I2.I4.I2-FZ
    gate I2.I4.I2 term FZ end
  end
  net .I2.I5.I2-AZ
    gate I2.I5.I2 term AZ end
  end
  net .I2.I5.I2-OZ
    gate I2.I5.I2 term OZ end
  end
  net .I2.I5.I2-NZ
    gate I2.I5.I2 term NZ end
  end
  net .I2.I5.I2-FZ
    gate I2.I5.I2 term FZ end
  end
  net .I2.I6.I2-AZ
    gate I2.I6.I2 term AZ end
  end
  net .I2.I6.I2-OZ
    gate I2.I6.I2 term OZ end
  end
  net .I2.I6.I2-NZ
    gate I2.I6.I2 term NZ end
  end
  net .I2.I6.I2-FZ
    gate I2.I6.I2 term FZ end
  end
  net .I2.I7.I2-AZ
    gate I2.I7.I2 term AZ end
  end
  net .I2.I7.I2-OZ
    gate I2.I7.I2 term OZ end
  end
  net .I2.I7.I2-NZ
    gate I2.I7.I2 term NZ end
  end
  net .I2.I7.I2-FZ
    gate I2.I7.I2 term FZ end
  end
  net .I2.I8.I2-AZ
    gate I2.I8.I2 term AZ end
  end
  net .I2.I8.I2-OZ
    gate I2.I8.I2 term OZ end
  end
  net .I2.I8.I2-NZ
    gate I2.I8.I2 term NZ end
  end
  net .I2.I8.I2-FZ
    gate I2.I8.I2 term FZ end
  end
  net .I2.I9.I2-AZ
    gate I2.I9.I2 term AZ end
  end
  net .I2.I9.I2-OZ
    gate I2.I9.I2 term OZ end
  end
  net .I2.I9.I2-NZ
    gate I2.I9.I2 term NZ end
  end
  net .I2.I9.I2-FZ
    gate I2.I9.I2 term FZ end
  end
  net .I3.I2-AZ
    gate I3.I2 term AZ end
  end
  net .I3.I2-OZ
    gate I3.I2 term OZ end
  end
  net .I3.I2-NZ
    gate I3.I2 term NZ end
  end
  net .I3.I2-FZ
    gate I3.I2 term FZ end
  end
  net .I12-enable_2
    gate I12.I11.I19 term QZ end
    gate I12.I10.I15 term F3 end
  end
  net .I12-enable_1
    gate I12.I11.I14 term QZ end
    gate I12.I11.I14 term F1 end
    gate I12.I10.I15 term F1 end
  end
  net .I12.I10-enable_in1
    gate I12.I10.I12 term F3 end
    gate I12.I10.I15 term FZ end
    gate I12.I10.I19.I18 term A1 end
  end
  net .I12.I10-enable_3
    gate I12.I10.I12 term F5 end
    gate I12.I10.I15 term QZ end
  end
  net .I12.I10-enable_4
    gate I12.I10.I12 term QZ end
  end
  net .I12.I10-enable_in2
    gate I12.I10.I12 term FZ end
    gate I12.I10.I20.I18 term A1 end
  end
  net .I12.I10-load_buf1
    gate I12.I10.I18 term AZ end
    gate I12.I10.I19.I3 term A2 end
  end
  net .I12.I10-load_buf2
    gate I12.I10.I18 term FZ end
    gate I12.I10.I20.I3 term A2 end
  end
  net .I12.I10-enable_buf
    gate I12.I10.I12 term F1 end
    gate I12.I10.I15 term F5 end
    gate I12.I10.I18 term NZ end
  end
  net .I12.I10.I12-AZ
    gate I12.I10.I12 term AZ end
  end
  net .I12.I10.I12-OZ
    gate I12.I10.I12 term OZ end
  end
  net .I12.I10.I12-NZ
    gate I12.I10.I12 term NZ end
  end
  net .I12.I10.I12-Q2Z
    gate I12.I10.I12 term Q2Z end
  end
  net .I12.I10.I15-AZ
    gate I12.I10.I15 term AZ end
  end
  net .I12.I10.I15-OZ
    gate I12.I10.I15 term OZ end