example_16bit_load.vq

VHDL examples for counter design, use QuickLogic eclips

wire \D3-OC_ ;
wire \D3-O1_ ;
wire \D3-NC_ ;
wire \D3-FI_ ;
wire \C3-Q2D_ ;
wire \C3-QCI_ ;
wire \C3-QD_ ;
wire \C3-O1_ ;
wire \E2-Q2D_ ;
wire \E2-QCI_ ;
wire \E2-QD_ ;
wire \E2-O1_ ;
wire \H1-Q2D_ ;
wire \H1-QCI_ ;
wire \H1-QD_ ;
wire \H1-O1_ ;
wire \G1-Q2D_ ;
wire \G1-QCI_ ;
wire \G1-QD_ ;
wire \G1-O1_ ;
wire \F1-Q2D_ ;
wire \F1-QCI_ ;
wire \F1-QD_ ;
wire \F1-O1_ ;
wire \E1-Q2D_ ;
wire \E1-QCI_ ;
wire \E1-QD_ ;
wire \E1-O1_ ;
wire \D1-Q2D_ ;
wire \D1-QCI_ ;
wire \D1-QD_ ;
wire \D1-O1_ ;
wire \C1-Q2D_ ;
wire \C1-QCI_ ;
wire \C1-QD_ ;
wire \C1-O1_ ;
wire load_LRBUF0;
wire \I12(I11(I25(I18-FZ ;
wire \I12(I11(I25(I18-NZ ;
wire \I12(I11(I25(I17-FZ ;
wire \I12(I11(I25(I17-NZ ;
wire \I12(I11(I25(I17-AZ ;
wire \I12(I11(I25(I16-FZ ;
wire \I12(I11(I25(I16-NZ ;
wire \I12(I11(I25(I16-AZ ;
wire \I12(I11(I25(I3-FZ ;
wire \I12(I11(I25(I3-NZ ;
wire \I12(I11(I25-Qb_r ;
wire \I12(I11(I25-Qa_r ;
wire \I12(I11(I25-Qb_a ;
wire \I12(I11(I25-Qa_a ;
wire \I12(I11(I25-Qc_a ;
wire \I12(I11(I25-Qc_r ;
wire \I12(I11(I25-enable_buf ;
wire \I12(I11(I25-Qd_r ;
wire \I12(I11(I25-Qd_a ;
wire \I12(I11(I25-load_N ;
wire \I12(I11(I24(I18-FZ ;
wire \I12(I11(I24(I18-NZ ;
wire \I12(I11(I24(I17-FZ ;
wire \I12(I11(I24(I17-NZ ;
wire \I12(I11(I24(I17-AZ ;
wire \I12(I11(I24(I16-FZ ;
wire \I12(I11(I24(I16-NZ ;
wire \I12(I11(I24(I16-AZ ;
wire \I12(I11(I24(I3-FZ ;
wire \I12(I11(I24(I3-NZ ;
wire \I12(I11(I24-Qb_r ;
wire \I12(I11(I24-Qa_r ;
wire \I12(I11(I24-Qb_a ;
wire \I12(I11(I24-Qa_a ;
wire \I12(I11(I24-Qc_a ;
wire \I12(I11(I24-Qc_r ;
wire \I12(I11(I24-enable_buf ;
wire \I12(I11(I24-Qd_r ;
wire \I12(I11(I24-Qd_a ;
wire \I12(I11(I24-load_N ;
wire \I12(I11(I23-Q2Z ;
wire \I12(I11(I23-NZ ;
wire \I12(I11(I23-QZ ;
wire \I12(I11(I23-OZ ;
wire \I12(I11(I19-Q2Z ;
wire \I12(I11(I19-NZ ;
wire \I12(I11(I19-OZ ;
wire \I12(I11(I19-AZ ;
wire \I12(I11(I14-Q2Z ;
wire \I12(I11(I14-NZ ;
wire \I12(I11(I14-OZ ;
wire \I12(I11(I14-AZ ;
wire \I12(I11-load_buf2 ;
wire \I12(I11-load_buf1 ;
wire \I12(I11-enable_buf ;
wire \I12(I11-enable_1 ;
wire \I12(I10(I20(I18-FZ ;
wire \I12(I10(I20(I18-NZ ;
wire \I12(I10(I20(I17-FZ ;
wire \I12(I10(I20(I17-NZ ;
wire \I12(I10(I20(I17-AZ ;
wire \I12(I10(I20(I16-FZ ;
wire \I12(I10(I20(I16-NZ ;
wire \I12(I10(I20(I16-AZ ;
wire \I12(I10(I20(I3-FZ ;
wire \I12(I10(I20(I3-NZ ;
wire \I12(I10(I20-Qb_r ;
wire \I12(I10(I20-Qa_r ;
wire \I12(I10(I20-Qb_a ;
wire \I12(I10(I20-Qa_a ;
wire \I12(I10(I20-Qc_a ;
wire \I12(I10(I20-Qc_r ;
wire \I12(I10(I20-enable_buf ;
wire \I12(I10(I20-Qd_r ;
wire \I12(I10(I20-Qd_a ;
wire \I12(I10(I20-load_N ;
wire \I12(I10(I19(I18-FZ ;
wire \I12(I10(I19(I18-NZ ;
wire \I12(I10(I19(I17-FZ ;
wire \I12(I10(I19(I17-NZ ;
wire \I12(I10(I19(I17-AZ ;
wire \I12(I10(I19(I16-FZ ;
wire \I12(I10(I19(I16-NZ ;
wire \I12(I10(I19(I16-AZ ;
wire \I12(I10(I19(I3-FZ ;
wire \I12(I10(I19(I3-NZ ;
wire \I12(I10(I19-Qb_r ;
wire \I12(I10(I19-Qa_r ;
wire \I12(I10(I19-Qb_a ;
wire \I12(I10(I19-Qa_a ;
wire \I12(I10(I19-Qc_a ;
wire \I12(I10(I19-Qc_r ;
wire \I12(I10(I19-enable_buf ;
wire \I12(I10(I19-Qd_r ;
wire \I12(I10(I19-Qd_a ;
wire \I12(I10(I19-load_N ;
wire \I12(I10(I18-Q2Z ;
wire \I12(I10(I18-QZ ;
wire \I12(I10(I18-OZ ;
wire \I12(I10(I15-Q2Z ;
wire \I12(I10(I15-NZ ;
wire \I12(I10(I15-OZ ;
wire \I12(I10(I15-AZ ;
wire \I12(I10(I12-Q2Z ;
wire \I12(I10(I12-NZ ;
wire \I12(I10(I12-OZ ;
wire \I12(I10(I12-AZ ;
wire \I12(I10-enable_buf ;
wire \I12(I10-load_buf2 ;
wire \I12(I10-load_buf1 ;
wire \I12(I10-enable_in2 ;
wire \I12(I10-enable_4 ;
wire \I12(I10-enable_3 ;
wire \I12(I10-enable_in1 ;
wire \I12-enable_1 ;
wire \I12-enable_2 ;
wire \I3(I2-FZ ;
wire \I3(I2-NZ ;
wire \I3(I2-OZ ;
wire \I3(I2-AZ ;
wire \I2(I9(I2-FZ ;
wire \I2(I9(I2-NZ ;
wire \I2(I9(I2-OZ ;
wire \I2(I9(I2-AZ ;
wire \I2(I8(I2-FZ ;
wire \I2(I8(I2-NZ ;
wire \I2(I8(I2-OZ ;
wire \I2(I8(I2-AZ ;
wire \I2(I7(I2-FZ ;
wire \I2(I7(I2-NZ ;
wire \I2(I7(I2-OZ ;
wire \I2(I7(I2-AZ ;
wire \I2(I6(I2-FZ ;
wire \I2(I6(I2-NZ ;
wire \I2(I6(I2-OZ ;
wire \I2(I6(I2-AZ ;
wire \I2(I5(I2-FZ ;
wire \I2(I5(I2-NZ ;
wire \I2(I5(I2-OZ ;
wire \I2(I5(I2-AZ ;
wire \I2(I4(I2-FZ ;
wire \I2(I4(I2-NZ ;
wire \I2(I4(I2-OZ ;
wire \I2(I4(I2-AZ ;
wire \I2(I3(I2-FZ ;
wire \I2(I3(I2-NZ ;
wire \I2(I3(I2-OZ ;
wire \I2(I3(I2-AZ ;
wire \I2(I2(I2-FZ ;
wire \I2(I2(I2-NZ ;
wire \I2(I2(I2-OZ ;
wire \I2(I2(I2-AZ ;
wire \I1(I9(I2-FZ ;
wire \I1(I9(I2-NZ ;
wire \I1(I9(I2-OZ ;
wire \I1(I9(I2-AZ ;
wire \I1(I8(I2-FZ ;
wire \I1(I8(I2-NZ ;
wire \I1(I8(I2-OZ ;
wire \I1(I8(I2-AZ ;
wire \I1(I7(I2-FZ ;
wire \I1(I7(I2-NZ ;
wire \I1(I7(I2-OZ ;
wire \I1(I7(I2-AZ ;
wire \I1(I6(I2-FZ ;
wire \I1(I6(I2-NZ ;
wire \I1(I6(I2-OZ ;
wire \I1(I6(I2-AZ ;
wire \I1(I5(I2-FZ ;
wire \I1(I5(I2-NZ ;
wire \I1(I5(I2-OZ ;
wire \I1(I5(I2-AZ ;
wire \I1(I4(I2-FZ ;
wire \I1(I4(I2-NZ ;
wire \I1(I4(I2-OZ ;
wire \I1(I4(I2-AZ ;
wire \I1(I3(I2-FZ ;
wire \I1(I3(I2-NZ ;
wire \I1(I3(I2-OZ ;
wire \I1(I3(I2-AZ ;
wire \I1(I2(I2-FZ ;
wire \I1(I2(I2-NZ ;
wire \I1(I2(I2-OZ ;
wire \I1(I2(I2-AZ ;
wire \data_reg[0] ;
wire \data_reg[1] ;
wire \data_reg[2] ;
wire \data_reg[3] ;
wire \data_reg[4] ;
wire \data_reg[5] ;
wire \data_reg[6] ;
wire \data_reg[7] ;
wire \data_reg[8] ;
wire \data_reg[9] ;
wire \data_reg[10] ;
wire \data_reg[11] ;
wire \data_reg[12] ;
wire \data_reg[13] ;
wire \data_reg[14] ;
wire \data_reg[15] ;
wire load_reg;
wire enable_reg;
wire \count_reg[0] ;
wire \count_reg[1] ;
wire \count_reg[2] ;
wire \count_reg[3] ;
wire \count_reg[4] ;
wire \count_reg[5] ;
wire \count_reg[6] ;
wire \count_reg[7] ;
wire \count_reg[8] ;
wire \count_reg[9] ;
wire \count_reg[10] ;
wire \count_reg[11] ;
wire \count_reg[12] ;
wire \count_reg[13] ;
wire \count_reg[14] ;
wire \count_reg[15] ;
wire \count[0] ;
wire \count[1] ;
wire \count[2] ;
wire \count[3] ;
wire \count[4] ;
wire \count[5] ;
wire \count[6] ;
wire \count[7] ;
wire \count[8] ;
wire \count[9] ;
wire \count[10] ;
wire \count[11] ;
wire \count[12] ;
wire \count[13] ;
wire \count[14] ;
wire \count[15] ;
wire clear;
wire \data_in[0] ;
wire \data_in[1] ;
wire \data_in[2] ;
wire \data_in[3] ;
wire \data_in[4] ;
wire \data_in[5] ;
wire \data_in[6] ;
wire \data_in[7] ;
wire \data_in[8] ;
wire \data_in[9] ;
wire \data_in[10] ;
wire \data_in[11] ;
wire \data_in[12] ;
wire \data_in[13] ;
wire \data_in[14] ;
wire \data_in[15] ;
wire load;
wire enable;
wire clk;

initial
begin
	$display("\nOPERATING RANGE: Commercial");
	$display("\nSPEED GRADE: 8\n");
end

P_BUF \I5(I3_IO307-FRAG_BIZ_BUF  (\IO307-INMUXZ_ ,\data_in[13] );
P_MUX2 \IO307-FRAG_BIN_MUX  (\IO307-VREFZ_ ,GND,\IO307-INPUTZ_ ,GND,VCC,
   \IO307-INMUXZ_ );
P_BUF \IO307-FRAG_BVREF  (\IO307-INPUTZ_ ,\IO307-VREFZ_ );
P_BUF \I5(I3_IO307-FRAG_BIDIR_PAD  (data[13],\IO307-INPUTZ_ );
P_BUF \I5(I15_IO306-FRAG_BIZ_BUF  (\IO306-INMUXZ_ ,\data_in[1] );
P_MUX2 \IO306-FRAG_BIN_MUX  (\IO306-VREFZ_ ,GND,\IO306-INPUTZ_ ,GND,VCC,
   \IO306-INMUXZ_ );
P_BUF \IO306-FRAG_BVREF  (\IO306-INPUTZ_ ,\IO306-VREFZ_ );
P_BUF \I5(I15_IO306-FRAG_BIDIR_PAD  (data[1],\IO306-INPUTZ_ );
P_BUF \I7_IO305-FRAG_BIZ_BUF  (\IO305-INMUXZ_ ,enable);
P_MUX2 \IO305-FRAG_BIN_MUX  (\IO305-VREFZ_ ,GND,\IO305-INPUTZ_ ,GND,VCC,
   \IO305-INMUXZ_ );
P_BUF \IO305-FRAG_BVREF  (\IO305-INPUTZ_ ,\IO305-VREFZ_ );
P_BUF \I7_IO305-FRAG_BIDIR_PAD  (enable_in,\IO305-INPUTZ_ );
P_BUF \I5(I4_IO304-FRAG_BIZ_BUF  (\IO304-INMUXZ_ ,\data_in[12] );
P_MUX2 \IO304-FRAG_BIN_MUX  (\IO304-VREFZ_ ,GND,\IO304-INPUTZ_ ,GND,VCC,