example_16bit_load.qdf

VHDL examples for counter design, use QuickLogic eclips

  net count[4]
    gate I2.I3.I2 term E1 end
    gate I12.I11.I19 term D1 end
    gate I12.I11.I24.I3 term Q2Z end
    gate I12.I11.I24.I3 term D1 end
    gate I12.I11.I24.I3 term E2 end
    gate I12.I11.I24.I18 term F1 end
  end
  net count[3]
    gate I2.I4.I2 term PS end
    gate I12.I11.I14 term A1 end
    gate I12.I11.I25.I16 term Q2Z end
  end
  net count[2]
    gate I2.I4.I2 term E1 end
    gate I12.I11.I14 term A3 end
    gate I12.I11.I25.I17 term Q2Z end
  end
  net count[1]
    gate I2.I5.I2 term PS end
    gate I12.I11.I14 term A5 end
    gate I12.I11.I25.I18 term Q2Z end
  end
  net count[0]
    gate I2.I5.I2 term E1 end
    gate I12.I11.I14 term E2 end
    gate I12.I11.I14 term D1 end
    gate I12.I11.I25.I3 term Q2Z end
    gate I12.I11.I25.I3 term D1 end
    gate I12.I11.I25.I3 term E2 end
    gate I12.I11.I25.I18 term F1 end
  end
  net count_reg[15]
    gate I4.I16 term A end
    gate I2.I6.I2 term Q2Z end
  end
  net count_reg[14]
    gate I4.I15 term A end
    gate I2.I6.I2 term QZ end
  end
  net count_reg[13]
    gate I4.I14 term A end
    gate I2.I7.I2 term Q2Z end
  end
  net count_reg[12]
    gate I4.I13 term A end
    gate I2.I7.I2 term QZ end
  end
  net count_reg[11]
    gate I4.I12 term A end
    gate I2.I8.I2 term Q2Z end
  end
  net count_reg[10]
    gate I4.I11 term A end
    gate I2.I8.I2 term QZ end
  end
  net count_reg[9]
    gate I4.I10 term A end
    gate I2.I9.I2 term Q2Z end
  end
  net count_reg[8]
    gate I4.I9 term A end
    gate I2.I9.I2 term QZ end
  end
  net count_reg[7]
    gate I4.I8 term A end
    gate I2.I2.I2 term Q2Z end
  end
  net count_reg[6]
    gate I4.I7 term A end
    gate I2.I2.I2 term QZ end
  end
  net count_reg[5]
    gate I4.I6 term A end
    gate I2.I3.I2 term Q2Z end
  end
  net count_reg[4]
    gate I4.I5 term A end
    gate I2.I3.I2 term QZ end
  end
  net count_reg[3]
    gate I4.I4 term A end
    gate I2.I4.I2 term Q2Z end
  end
  net count_reg[2]
    gate I4.I3 term A end
    gate I2.I4.I2 term QZ end
  end
  net count_reg[1]
    gate I4.I2 term A end
    gate I2.I5.I2 term Q2Z end
  end
  net count_reg[0]
    gate I4.I1 term A end
    gate I2.I5.I2 term QZ end
  end
  net enable_reg
    gate I3.I2 term QZ end
    gate I12.I11.I19 term F1 end
    gate I12.I10.I18 term D1 end
  end
  net load_reg
    gate I3.I2 term Q2Z end
  end
  net data[15] direction input
    gate I5.I1 term P end
  end
  net data[14] direction input
    gate I5.I2 term P end
  end
  net data[13] direction input
    gate I5.I3 term P end
  end
  net data[12] direction input
    gate I5.I4 term P end
  end
  net data[11] direction input
    gate I5.I8 term P end
  end
  net data[10] direction input
    gate I5.I7 term P end
  end
  net data[9] direction input
    gate I5.I6 term P end
  end
  net data[8] direction input
    gate I5.I5 term P end
  end
  net data[7] direction input
    gate I5.I9 term P end
  end
  net data[6] direction input
    gate I5.I10 term P end
  end
  net data[5] direction input
    gate I5.I11 term P end
  end
  net data[4] direction input
    gate I5.I12 term P end
  end
  net data[3] direction input
    gate I5.I13 term P end
  end
  net data[2] direction input
    gate I5.I14 term P end
  end
  net data[1] direction input
    gate I5.I15 term P end
  end
  net data[0] direction input
    gate I5.I16 term P end
  end
  net count_out[15] direction output
    gate I4.I16 term P end
  end
  net count_out[14] direction output
    gate I4.I15 term P end
  end
  net count_out[13] direction output
    gate I4.I14 term P end
  end
  net count_out[12] direction output
    gate I4.I13 term P end
  end
  net count_out[11] direction output
    gate I4.I12 term P end
  end
  net count_out[10] direction output
    gate I4.I11 term P end
  end
  net count_out[9] direction output
    gate I4.I10 term P end
  end
  net count_out[8] direction output
    gate I4.I9 term P end
  end
  net count_out[7] direction output
    gate I4.I8 term P end
  end
  net count_out[6] direction output
    gate I4.I7 term P end
  end
  net count_out[5] direction output
    gate I4.I6 term P end
  end
  net count_out[4] direction output
    gate I4.I5 term P end
  end
  net count_out[3] direction output
    gate I4.I4 term P end
  end
  net count_out[2] direction output
    gate I4.I3 term P end
  end
  net count_out[1] direction output
    gate I4.I2 term P end
  end
  net count_out[0] direction output
    gate I4.I1 term P end
  end
  net clk_in direction input
    gate I9 term P end
  end
  net clear_in direction input
    gate I8 term P end
  end
  net enable_in direction input
    gate I7 term P end
  end
  net load_in direction input
    gate I6 term P end
  end
  net data_reg[15]
    gate I1.I6.I2 term Q2Z end
    gate I12.I10.I20.I16 term B1 end
  end
  net data_reg[14]
    gate I1.I6.I2 term QZ end
    gate I12.I10.I20.I17 term B1 end
  end
  net data_reg[13]
    gate I1.I7.I2 term Q2Z end
    gate I12.I10.I20.I18 term B1 end
  end
  net data_reg[12]
    gate I1.I7.I2 term QZ end
    gate I12.I10.I20.I3 term B1 end
  end
  net data_reg[11]
    gate I1.I8.I2 term Q2Z end
    gate I12.I10.I19.I16 term B1 end
  end
  net data_reg[10]
    gate I1.I8.I2 term QZ end
    gate I12.I10.I19.I17 term B1 end
  end
  net data_reg[9]
    gate I1.I9.I2 term Q2Z end
    gate I12.I10.I19.I18 term B1 end
  end
  net data_reg[8]
    gate I1.I9.I2 term QZ end
    gate I12.I10.I19.I3 term B1 end
  end
  net data_reg[7]
    gate I1.I2.I2 term Q2Z end
    gate I12.I11.I24.I16 term B1 end
  end
  net data_reg[6]
    gate I1.I2.I2 term QZ end
    gate I12.I11.I24.I17 term B1 end
  end
  net data_reg[5]
    gate I1.I3.I2 term Q2Z end
    gate I12.I11.I24.I18 term B1 end
  end
  net data_reg[4]
    gate I1.I3.I2 term QZ end
    gate I12.I11.I24.I3 term B1 end
  end
  net data_reg[3]
    gate I1.I4.I2 term Q2Z end
    gate I12.I11.I25.I16 term B1 end
  end
  net data_reg[2]
    gate I1.I4.I2 term QZ end
    gate I12.I11.I25.I17 term B1 end
  end
  net data_reg[1]
    gate I1.I5.I2 term Q2Z end
    gate I12.I11.I25.I18 term B1 end
  end
  net data_reg[0]
    gate I1.I5.I2 term QZ end
    gate I12.I11.I25.I3 term B1 end
  end
  net .I1.I2.I2-AZ direction output
    gate I1.I2.I2 term AZ end
  end
  net .I1.I2.I2-OZ direction output
    gate I1.I2.I2 term OZ end
  end
  net .I1.I2.I2-NZ direction output
    gate I1.I2.I2 term NZ end
  end
  net .I1.I2.I2-FZ direction output
    gate I1.I2.I2 term FZ end
  end
  net .I1.I3.I2-AZ direction output
    gate I1.I3.I2 term AZ end
  end
  net .I1.I3.I2-OZ direction output
    gate I1.I3.I2 term OZ end
  end
  net .I1.I3.I2-NZ direction output
    gate I1.I3.I2 term NZ end
  end
  net .I1.I3.I2-FZ direction output
    gate I1.I3.I2 term FZ end
  end
  net .I1.I4.I2-AZ direction output
    gate I1.I4.I2 term AZ end
  end
  net .I1.I4.I2-OZ direction output
    gate I1.I4.I2 term OZ end
  end
  net .I1.I4.I2-NZ direction output
    gate I1.I4.I2 term NZ end
  end
  net .I1.I4.I2-FZ direction output
    gate I1.I4.I2 term FZ end
  end
  net .I1.I5.I2-AZ direction output
    gate I1.I5.I2 term AZ end
  end
  net .I1.I5.I2-OZ direction output
    gate I1.I5.I2 term OZ end
  end
  net .I1.I5.I2-NZ direction output
    gate I1.I5.I2 term NZ end
  end
  net .I1.I5.I2-FZ direction output
    gate I1.I5.I2 term FZ end
  end
  net .I1.I6.I2-AZ direction output
    gate I1.I6.I2 term AZ end
  end
  net .I1.I6.I2-OZ direction output
    gate I1.I6.I2 term OZ end
  end
  net .I1.I6.I2-NZ direction output
    gate I1.I6.I2 term NZ end
  end
  net .I1.I6.I2-FZ direction output
    gate I1.I6.I2 term FZ end
  end
  net .I1.I7.I2-AZ direction output
    gate I1.I7.I2 term AZ end
  end
  net .I1.I7.I2-OZ direction output
    gate I1.I7.I2 term OZ end
  end
  net .I1.I7.I2-NZ direction output
    gate I1.I7.I2 term NZ end
  end
  net .I1.I7.I2-FZ direction output
    gate I1.I7.I2 term FZ end
  end
  net .I1.I8.I2-AZ direction output
    gate I1.I8.I2 term AZ end
  end
  net .I1.I8.I2-OZ direction output
    gate I1.I8.I2 term OZ end
  end
  net .I1.I8.I2-NZ direction output
    gate I1.I8.I2 term NZ end
  end
  net .I1.I8.I2-FZ direction output
    gate I1.I8.I2 term FZ end
  end
  net .I1.I9.I2-AZ direction output
    gate I1.I9.I2 term AZ end
  end
  net .I1.I9.I2-OZ direction output
    gate I1.I9.I2 term OZ end
  end
  net .I1.I9.I2-NZ direction output
    gate I1.I9.I2 term NZ end
  end
  net .I1.I9.I2-FZ direction output
    gate I1.I9.I2 term FZ end
  end
  net .I2.I2.I2-AZ direction output
    gate I2.I2.I2 term AZ end
  end
  net .I2.I2.I2-OZ direction output
    gate I2.I2.I2 term OZ end
  end
  net .I2.I2.I2-NZ direction output
    gate I2.I2.I2 term NZ end
  end
  net .I2.I2.I2-FZ direction output
    gate I2.I2.I2 term FZ end
  end
  net .I2.I3.I2-AZ direction output
    gate I2.I3.I2 term AZ end
  end
  net .I2.I3.I2-OZ direction output
    gate I2.I3.I2 term OZ end
  end
  net .I2.I3.I2-NZ direction output
    gate I2.I3.I2 term NZ end
  end
  net .I2.I3.I2-FZ direction output
    gate I2.I3.I2 term FZ end
  end
  net .I2.I4.I2-AZ direction output
    gate I2.I4.I2 term AZ end
  end
  net .I2.I4.I2-OZ direction output
    gate I2.I4.I2 term OZ end
  end
  net .I2.I4.I2-NZ direction output
    gate I2.I4.I2 term NZ end
  end
  net .I2.I4.I2-FZ direction output
    gate I2.I4.I2 term FZ end
  end
  net .I2.I5.I2-AZ direction output
    gate I2.I5.I2 term AZ end
  end
  net .I2.I5.I2-OZ direction output
    gate I2.I5.I2 term OZ end
  end
  net .I2.I5.I2-NZ direction output
    gate I2.I5.I2 term NZ end
  end
  net .I2.I5.I2-FZ direction output
    gate I2.I5.I2 term FZ end
  end
  net .I2.I6.I2-AZ direction output
    gate I2.I6.I2 term AZ end
  end
  net .I2.I6.I2-OZ direction output
    gate I2.I6.I2 term OZ end
  end
  net .I2.I6.I2-NZ direction output
    gate I2.I6.I2 term NZ end
  end
  net .I2.I6.I2-FZ direction output
    gate I2.I6.I2 term FZ end
  end
  net .I2.I7.I2-AZ direction output
    gate I2.I7.I2 term AZ end
  end
  net .I2.I7.I2-OZ direction output
    gate I2.I7.I2 term OZ end
  end
  net .I2.I7.I2-NZ direction output