example_8bit_load.chp

VHDL examples for counter design, use QuickLogic eclips

      port OS net GND
      port PS net .I12.I22-Qd_a
      port QR net clear
    end
  end
  cell A4
    gate I1.I4.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[5]
      port QZ net count_reg[4]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[4]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[5]
    end
  end
  cell C4
    gate I12.I22.I16
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term F5 port F5 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments FONQS;
      port OZ net .I12.I22-Qa_a
      port Q2Z net count[7]
      port QZ net .I12.I22-Qa_r
      port DCLK net clk
      port CLKSEL net GND
      port B1 net data_reg[7]
      port C1 net GND
      port D1 net .I12.I22-Qa_r
      port E2 net .I12.I22-Qa_r
      port F1 net .I12.I22-Qb_r
      port F3 net .I12.I22-Qc_r
      port F5 net .I12.I22-Qd_r
      port MP net GND
      port MS net GND
      port NP net .I12.I22-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12.I22-load_N
      port PS net .I12.I22-Qa_a
      port QR net clear
    end
  end
  cell D4
    gate I12.I22.I18
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term AZ port AZ end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I12.I22-enable_buf
      port OZ net .I12.I22-Qc_a
      port Q2Z net count[5]
      port QZ net .I12.I22-Qc_r
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I12-enable_1
      port B1 net data_reg[5]
      port C1 net GND
      port D1 net .I12.I22-Qc_r
      port E2 net .I12.I22-Qc_r
      port F1 net count[4]
      port MP net GND
      port MS net GND
      port NP net .I12.I22-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12.I22-load_N
      port PS net .I12.I22-Qc_a
      port QR net clear
    end
  end
  cell A5
    gate I1.I6.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[3]
      port QZ net count_reg[2]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[2]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[3]
    end
  end
  cell B5
    gate I3.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net load_reg
      port QZ net enable_reg
      port DCLK net clk
      port CLKSEL net GND
      port E1 net enable
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net load
    end
  end
  cell C5
    gate I12.I19
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term D1 port D1 end
      term E1 port E1 end
      term F1 port F1 end
      term NP port NP end
      term NS port NS end
      term FZ port FZ end
    end
    block fragments AFN;
      port FZ net .I12-enable_buf
      port A1 net count[7]
      port A3 net count[6]
      port A5 net count[5]
      port D1 net count[4]
      port E1 net GND
      port F1 net enable_reg
      port NP net GND
      port NS net GND
    end
  end
  cell D5
    gate I12.I14
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term A3 port A3 end
      term A5 port A5 end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OS port OS end
      term QR port QR end
      term FZ port FZ end
      term QZ port QZ end
    end
    block fragments AFONQ;
      port FZ net .I12-enable_1
      port QZ net .I12-fo_enable
      port DCLK net clk
      port CLKSEL net GND
      port A1 net count[3]
      port A3 net count[2]
      port A5 net count[1]
      port B1 net GND
      port C1 net GND
      port D1 net count[0]
      port E2 net count[0]
      port F1 net .I12-fo_enable
      port F3 net .I12-enable_buf
      port MP net GND
      port MS net GND
      port NP net GND
      port NS net .I12-enable_buf
      port OS net GND
      port QR net clear
    end
  end
  cell A6
    gate I1.I5.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net count_reg[1]
      port QZ net count_reg[0]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net count[0]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net count[1]
    end
  end
  cell C6
    gate I12.I23.I16
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term F5 port F5 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments FONQS;
      port OZ net .I12.I23-Qa_a
      port Q2Z net count[3]
      port QZ net .I12.I23-Qa_r
      port DCLK net clk
      port CLKSEL net GND
      port B1 net data_reg[3]
      port C1 net GND
      port D1 net .I12.I23-Qa_r
      port E2 net .I12.I23-Qa_r
      port F1 net .I12.I23-Qb_r
      port F3 net .I12.I23-Qc_r
      port F5 net .I12.I23-Qd_r
      port MP net GND
      port MS net GND
      port NP net .I12.I23-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12.I23-load_N
      port PS net .I12.I23-Qa_a
      port QR net clear
    end
  end
  cell D6
    gate I12.I23.I18
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A1 port A1 end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term AZ port AZ end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I12.I23-enable_buf
      port OZ net .I12.I23-Qc_a
      port Q2Z net count[1]
      port QZ net .I12.I23-Qc_r
      port DCLK net clk
      port CLKSEL net GND
      port A1 net .I12-enable_buf
      port B1 net data_reg[1]
      port C1 net GND
      port D1 net .I12.I23-Qc_r
      port E2 net .I12.I23-Qc_r
      port F1 net count[0]
      port MP net GND
      port MS net GND
      port NP net .I12.I23-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12.I23-load_N
      port PS net .I12.I23-Qc_a
      port QR net clear
    end
  end
  cell A7
    gate I2.I5.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments ONQS;
      port Q2Z net data_reg[1]
      port QZ net data_reg[0]
      port DCLK net clk
      port CLKSEL net GND
      port E1 net data_in[0]
      port MP net GND
      port NP net GND
      port OP net GND
      port PS net data_in[1]
    end
  end
  cell C7
    gate I12.I23.I17
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term F1 port F1 end
      term F3 port F3 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OP port OP end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments FONQS;
      port OZ net .I12.I23-Qb_a
      port Q2Z net count[2]
      port QZ net .I12.I23-Qb_r
      port DCLK net clk
      port CLKSEL net GND
      port B1 net data_reg[2]
      port C1 net GND
      port D1 net .I12.I23-Qb_r
      port E2 net .I12.I23-Qb_r
      port F1 net .I12.I23-Qc_r
      port F3 net .I12.I23-Qd_r
      port MP net GND
      port MS net GND
      port NP net .I12.I23-enable_buf
      port NS net GND
      port OP net GND
      port OS net .I12.I23-load_N
      port PS net .I12.I23-Qb_a
      port QR net clear
    end
  end
  cell D7
    gate I12.I23.I3
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term A2 port A2 end
      term B1 port B1 end
      term C1 port C1 end
      term D1 port D1 end
      term E2 port E2 end
      term MP port MP end
      term MS port MS end
      term NP port NP end
      term NS port NS end
      term OS port OS end
      term PS port PS end
      term QR port QR end
      term AZ port AZ end
      term OZ port OZ end
      term Q2Z port Q2Z end
      term QZ port QZ end
    end
    block fragments AFONQS;
      port AZ net .I12.I23-load_N
      port OZ net .I12.I23-Qd_a
      port Q2Z net count[0]
      port QZ net .I12.I23-Qd_r
      port DCLK net clk
      port CLKSEL net GND
      port A2 net load_reg
      port B1 net data_reg[0]
      port C1 net GND
      port D1 net count[0]
      port E2 net count[0]
      port MP net GND
      port MS net GND
      port NP net .I12.I23-enable_buf
      port NS net GND
      port OS net GND
      port PS net .I12.I23-Qd_a
      port QR net clear
    end
  end
  cell C8
    gate I2.I6.I2
      term DCLK port DCLK end
      term CLKSEL port CLKSEL end
      term E1 port E1 end
      term MP port MP end
      term NP port NP end
      term OP port OP end
      term PS port PS end
      term Q2Z port Q2Z end
      term QZ port QZ