example_8bit_load.vhh

来自「VHDL examples for counter design, use Qu」· VHH 代码 · 共 10 行

entity example_8bit_load is
      Port ( clear_in : In    STD_LOGIC;
              clk_in : In    STD_LOGIC;
                data : In    STD_LOGIC_VECTOR (7 downto 0);
             enable_in : In    STD_LOGIC;
             load_in : In    STD_LOGIC;
             count_out : Out   STD_LOGIC_VECTOR (7 downto 0) );
end example_8bit_load;