example_24bit_load.qdf

VHDL examples for counter design, use QuickLogic eclips

  net count[0]
    gate I2.I5.I2 term E1 end
    gate I14.I8.I11.I14 term E2 end
    gate I14.I8.I11.I14 term D1 end
    gate I14.I8.I11.I25.I3 term Q2Z end
    gate I14.I8.I11.I25.I3 term D1 end
    gate I14.I8.I11.I25.I3 term E2 end
    gate I14.I8.I11.I25.I18 term F1 end
  end
  net count_reg[15]
    gate I2.I6.I2 term Q2Z end
    gate outpad_25um[15] term A end
  end
  net count_reg[14]
    gate I2.I6.I2 term QZ end
    gate outpad_25um[14] term A end
  end
  net count_reg[13]
    gate I2.I7.I2 term Q2Z end
    gate outpad_25um[13] term A end
  end
  net count_reg[12]
    gate I2.I7.I2 term QZ end
    gate outpad_25um[12] term A end
  end
  net count_reg[11]
    gate I2.I8.I2 term Q2Z end
    gate outpad_25um[11] term A end
  end
  net count_reg[10]
    gate I2.I8.I2 term QZ end
    gate outpad_25um[10] term A end
  end
  net count_reg[9]
    gate I2.I9.I2 term Q2Z end
    gate outpad_25um[9] term A end
  end
  net count_reg[8]
    gate I2.I9.I2 term QZ end
    gate outpad_25um[8] term A end
  end
  net count_reg[7]
    gate I2.I2.I2 term Q2Z end
    gate outpad_25um[7] term A end
  end
  net count_reg[6]
    gate I2.I2.I2 term QZ end
    gate outpad_25um[6] term A end
  end
  net count_reg[5]
    gate I2.I3.I2 term Q2Z end
    gate outpad_25um[5] term A end
  end
  net count_reg[4]
    gate I2.I3.I2 term QZ end
    gate outpad_25um[4] term A end
  end
  net count_reg[3]
    gate I2.I4.I2 term Q2Z end
    gate outpad_25um[3] term A end
  end
  net count_reg[2]
    gate I2.I4.I2 term QZ end
    gate outpad_25um[2] term A end
  end
  net count_reg[1]
    gate I2.I5.I2 term Q2Z end
    gate outpad_25um[1] term A end
  end
  net count_reg[0]
    gate I2.I5.I2 term QZ end
    gate outpad_25um[0] term A end
  end
  net enable_reg
    gate I3.I2 term QZ end
    gate I14.I9.I16 term A1 end
    gate I14.I8.I10.I18 term D1 end
    gate I14.I8.I11.I19 term F1 end
  end
  net load_reg
    gate I3.I2 term Q2Z end
    gate I14.I9.I12 term F1 end
    gate I14.I9.I15 term F1 end
    gate I14.I8.I10.I18 term F1 end
    gate I14.I8.I10.I18 term A5 end
    gate I14.I8.I11.I23 term A1 end
    gate I14.I8.I11.I23 term F1 end
  end
  net clk_in direction input
    gate I9 term P end
  end
  net clear_in direction input
    gate I8 term P end
  end
  net enable_in direction input
    gate I7 term P end
  end
  net load_in direction input
    gate I6 term P end
  end
  net data_reg[15]
    gate I1.I6.I2 term Q2Z end
    gate I14.I8.I10.I20.I16 term B1 end
  end
  net data_reg[14]
    gate I1.I6.I2 term QZ end
    gate I14.I8.I10.I20.I17 term B1 end
  end
  net data_reg[13]
    gate I1.I7.I2 term Q2Z end
    gate I14.I8.I10.I20.I18 term B1 end
  end
  net data_reg[12]
    gate I1.I7.I2 term QZ end
    gate I14.I8.I10.I20.I3 term B1 end
  end
  net data_reg[11]
    gate I1.I8.I2 term Q2Z end
    gate I14.I8.I10.I19.I16 term B1 end
  end
  net data_reg[10]
    gate I1.I8.I2 term QZ end
    gate I14.I8.I10.I19.I17 term B1 end
  end
  net data_reg[9]
    gate I1.I9.I2 term Q2Z end
    gate I14.I8.I10.I19.I18 term B1 end
  end
  net data_reg[8]
    gate I1.I9.I2 term QZ end
    gate I14.I8.I10.I19.I3 term B1 end
  end
  net data_reg[7]
    gate I1.I2.I2 term Q2Z end
    gate I14.I8.I11.I24.I16 term B1 end
  end
  net data_reg[6]
    gate I1.I2.I2 term QZ end
    gate I14.I8.I11.I24.I17 term B1 end
  end
  net data_reg[5]
    gate I1.I3.I2 term Q2Z end
    gate I14.I8.I11.I24.I18 term B1 end
  end
  net data_reg[4]
    gate I1.I3.I2 term QZ end
    gate I14.I8.I11.I24.I3 term B1 end
  end
  net data_reg[3]
    gate I1.I4.I2 term Q2Z end
    gate I14.I8.I11.I25.I16 term B1 end
  end
  net data_reg[2]
    gate I1.I4.I2 term QZ end
    gate I14.I8.I11.I25.I17 term B1 end
  end
  net data_reg[1]
    gate I1.I5.I2 term Q2Z end
    gate I14.I8.I11.I25.I18 term B1 end
  end
  net data_reg[0]
    gate I1.I5.I2 term QZ end
    gate I14.I8.I11.I25.I3 term B1 end
  end
  net count_reg[23]
    gate I13.QL8 term Q end
    gate outpad_25um[23] term A end
  end
  net count_reg[22]
    gate I13.QL1 term Q end
    gate outpad_25um[22] term A end
  end
  net count_reg[21]
    gate I13.QL2 term Q end
    gate outpad_25um[21] term A end
  end
  net count_reg[20]
    gate I13.QL3 term Q end
    gate outpad_25um[20] term A end
  end
  net count_reg[19]
    gate I13.QL4 term Q end
    gate outpad_25um[19] term A end
  end
  net count_reg[18]
    gate I13.QL5 term Q end
    gate outpad_25um[18] term A end
  end
  net count_reg[17]
    gate I13.QL6 term Q end
    gate outpad_25um[17] term A end
  end
  net count_reg[16]
    gate I13.QL7 term Q end
    gate outpad_25um[16] term A end
  end
  net count_out[23] direction output
    gate outpad_25um[23] term P end
  end
  net count_out[22] direction output
    gate outpad_25um[22] term P end
  end
  net count_out[21] direction output
    gate outpad_25um[21] term P end
  end
  net count_out[20] direction output
    gate outpad_25um[20] term P end
  end
  net count_out[19] direction output
    gate outpad_25um[19] term P end
  end
  net count_out[18] direction output
    gate outpad_25um[18] term P end
  end
  net count_out[17] direction output
    gate outpad_25um[17] term P end
  end
  net count_out[16] direction output
    gate outpad_25um[16] term P end
  end
  net count_out[15] direction output
    gate outpad_25um[15] term P end
  end
  net count_out[14] direction output
    gate outpad_25um[14] term P end
  end
  net count_out[13] direction output
    gate outpad_25um[13] term P end
  end
  net count_out[12] direction output
    gate outpad_25um[12] term P end
  end
  net count_out[11] direction output
    gate outpad_25um[11] term P end
  end
  net count_out[10] direction output
    gate outpad_25um[10] term P end
  end
  net count_out[9] direction output
    gate outpad_25um[9] term P end
  end
  net count_out[8] direction output
    gate outpad_25um[8] term P end
  end
  net count_out[7] direction output
    gate outpad_25um[7] term P end
  end
  net count_out[6] direction output
    gate outpad_25um[6] term P end
  end
  net count_out[5] direction output
    gate outpad_25um[5] term P end
  end
  net count_out[4] direction output
    gate outpad_25um[4] term P end
  end
  net count_out[3] direction output
    gate outpad_25um[3] term P end
  end
  net count_out[2] direction output
    gate outpad_25um[2] term P end
  end
  net count_out[1] direction output
    gate outpad_25um[1] term P end
  end
  net count_out[0] direction output
    gate outpad_25um[0] term P end
  end
  net data[23] direction input
    gate inpad_25um[23] term P end
  end
  net data[22] direction input
    gate inpad_25um[22] term P end
  end
  net data[21] direction input
    gate inpad_25um[21] term P end
  end
  net data[20] direction input
    gate inpad_25um[20] term P end
  end
  net data[19] direction input
    gate inpad_25um[19] term P end
  end
  net data[18] direction input
    gate inpad_25um[18] term P end
  end
  net data[17] direction input
    gate inpad_25um[17] term P end
  end
  net data[16] direction input
    gate inpad_25um[16] term P end
  end
  net data[15] direction input
    gate inpad_25um[15] term P end
  end
  net data[14] direction input
    gate inpad_25um[14] term P end
  end
  net data[13] direction input
    gate inpad_25um[13] term P end
  end
  net data[12] direction input
    gate inpad_25um[12] term P end
  end
  net data[11] direction input
    gate inpad_25um[11] term P end
  end
  net data[10] direction input
    gate inpad_25um[10] term P end
  end
  net data[9] direction input
    gate inpad_25um[9] term P end
  end
  net data[8] direction input
    gate inpad_25um[8] term P end
  end
  net data[7] direction input
    gate inpad_25um[7] term P end
  end
  net data[6] direction input
    gate inpad_25um[6] term P end
  end
  net data[5] direction input
    gate inpad_25um[5] term P end
  end
  net data[4] direction input
    gate inpad_25um[4] term P end
  end
  net data[3] direction input
    gate inpad_25um[3] term P end
  end
  net data[2] direction input
    gate inpad_25um[2] term P end
  end
  net data[1] direction input
    gate inpad_25um[1] term P end
  end
  net data[0] direction input
    gate inpad_25um[0] term P end
  end
  net data_in[23]
    gate inpad_25um[23] term Q end
    gate I12.QL8 term D end
  end
  net data_in[22]
    gate inpad_25um[22] term Q end
    gate I12.QL1 term D end
  end
  net data_in[21]
    gate inpad_25um[21] term Q end
    gate I12.QL2 term D end
  end
  net data_in[20]
    gate inpad_25um[20] term Q end
    gate I12.QL3 term D end
  end
  net data_in[19]
    gate inpad_25um[19] term Q end
    gate I12.QL4 term D end
  end
  net data_in[18]
    gate inpad_25um[18] term Q end
    gate I12.QL5 term D end
  end
  net data_in[17]
    gate inpad_25um[17] term Q end
    gate I12.QL6 term D end
  end
  net data_in[16]
    gate inpad_25um[16] term Q end
    gate I12.QL7 term D end
  end
  net data_in[15]
    gate inpad_25um[15] term Q end
    gate I1.I6.I2 term PS end
  end
  net data_in[14]
    gate inpad_25um[14] term Q end
    gate I1.I6.I2 term E1 end
  end
  net data_in[13]
    gate inpad_25um[13] term Q end
    gate I1.I7.I2 term PS end
  end
  net data_in[12]
    gate inpad_25um[12] term Q end
    gate I1.I7.I2 term E1 end
  end
  net data_in[11]
    gate inpad_25um[11] term Q end
    gate I1.I8.I2 term PS end
  end
  net data_in[10]
    gate inpad_25um[10] term Q end
    gate I1.I8.I2 term E1 end
  end
  net data_in[9