example_en_32bit_a.qdf

VHDL examples for counter design, use QuickLogic eclips

    gate I9.I15.I6.I5.I1 term C1 end
    gate I9.I15.I6.I5.I1 term QZ end
  end
  net count[8]
    gate I5.I9.I2 term E1 end
    gate I9.I2 term F3 end
    gate I9.I15.I6.I5.I2 term Q2Z end
    gate I9.I15.I6.I5.I2 term D2 end
    gate I9.I15.I6.I5.I2 term E1 end
    gate I9.I15.I6.I5.I2 term F5 end
    gate I9.I15.I6.I5.I1 term F3 end
    gate I9.I15.I6.I5.I2 term NS end
  end
  net count[7]
    gate I5.I2.I2 term PS end
    gate I9.I2 term F5 end
    gate I9.I15.I7.I1 term F3 end
    gate I9.I15.I7.I9.I2 term QZ end
    gate I9.I15.I7.I9.I2 term B1 end
    gate I9.I15.I7.I9.I2 term C2 end
    gate I9.I15.I7.I9.I1 term A5 end
  end
  net count[6]
    gate I5.I2.I2 term E1 end
    gate I9.I1 term A1 end
    gate I9.I15.I7.I1 term F1 end
    gate I9.I15.I7.I9.I2 term F1 end
    gate I9.I15.I7.I9.I1 term D1 end
    gate I9.I15.I7.I9.I1 term E2 end
    gate I9.I15.I7.I9.I1 term Q2Z end
  end
  net count[5]
    gate I5.I3.I2 term PS end
    gate I9.I1 term A3 end
    gate I9.I15.I7.I2 term A5 end
    gate I9.I15.I7.I9.I1 term NP end
    gate I9.I15.I7.I9.I2 term F3 end
    gate I9.I15.I7.I9.I1 term MS end
    gate I9.I15.I7.I9.I1 term B2 end
    gate I9.I15.I7.I9.I1 term C1 end
    gate I9.I15.I7.I9.I1 term QZ end
  end
  net count[4]
    gate I5.I3.I2 term E1 end
    gate I9.I1 term A5 end
    gate I9.I15.I7.I2 term A3 end
    gate I9.I15.I7.I9.I2 term Q2Z end
    gate I9.I15.I7.I9.I2 term D2 end
    gate I9.I15.I7.I9.I2 term E1 end
    gate I9.I15.I7.I9.I2 term F5 end
    gate I9.I15.I7.I9.I1 term F3 end
    gate I9.I15.I7.I9.I2 term NS end
  end
  net count[3]
    gate I5.I4.I2 term PS end
    gate I9.I1 term OP end
    gate I9.I15.I7.I2 term A1 end
    gate I9.I15.I7.I8.I2 term QZ end
    gate I9.I15.I7.I8.I2 term B1 end
    gate I9.I15.I7.I8.I2 term C2 end
    gate I9.I15.I7.I8.I1 term A5 end
  end
  net count[2]
    gate I5.I4.I2 term E1 end
    gate I9.I1 term E1 end
    gate I9.I15.I7.I1 term A5 end
    gate I9.I15.I7.I8.I2 term F1 end
    gate I9.I15.I7.I8.I1 term D1 end
    gate I9.I15.I7.I8.I1 term E2 end
    gate I9.I15.I7.I8.I1 term Q2Z end
  end
  net count[1]
    gate I5.I5.I2 term PS end
    gate I9.I1 term NP end
    gate I9.I15.I7.I1 term A3 end
    gate I9.I15.I7.I8.I1 term NP end
    gate I9.I15.I7.I8.I2 term F3 end
    gate I9.I15.I7.I8.I1 term MS end
    gate I9.I15.I7.I8.I1 term B2 end
    gate I9.I15.I7.I8.I1 term C1 end
    gate I9.I15.I7.I8.I1 term QZ end
  end
  net count[0]
    gate I5.I5.I2 term E1 end
    gate I9.I1 term F1 end
    gate I9.I15.I7.I1 term A1 end
    gate I9.I15.I7.I8.I2 term Q2Z end
    gate I9.I15.I7.I8.I2 term D2 end
    gate I9.I15.I7.I8.I2 term E1 end
    gate I9.I15.I7.I8.I2 term F5 end
    gate I9.I15.I7.I8.I1 term F3 end
    gate I9.I15.I7.I8.I2 term NS end
  end
  net count_reg[31]
    gate out_pad_25um[31] term A end
    gate I6.I6.I2 term Q2Z end
  end
  net count_reg[30]
    gate out_pad_25um[30] term A end
    gate I6.I6.I2 term QZ end
  end
  net count_reg[29]
    gate out_pad_25um[29] term A end
    gate I6.I7.I2 term Q2Z end
  end
  net count_reg[28]
    gate out_pad_25um[28] term A end
    gate I6.I7.I2 term QZ end
  end
  net count_reg[27]
    gate out_pad_25um[27] term A end
    gate I6.I8.I2 term Q2Z end
  end
  net count_reg[26]
    gate out_pad_25um[26] term A end
    gate I6.I8.I2 term QZ end
  end
  net count_reg[25]
    gate out_pad_25um[25] term A end
    gate I6.I9.I2 term Q2Z end
  end
  net count_reg[24]
    gate out_pad_25um[24] term A end
    gate I6.I9.I2 term QZ end
  end
  net count_reg[23]
    gate out_pad_25um[23] term A end
    gate I6.I2.I2 term Q2Z end
  end
  net count_reg[22]
    gate out_pad_25um[22] term A end
    gate I6.I2.I2 term QZ end
  end
  net count_reg[21]
    gate out_pad_25um[21] term A end
    gate I6.I3.I2 term Q2Z end
  end
  net count_reg[20]
    gate out_pad_25um[20] term A end
    gate I6.I3.I2 term QZ end
  end
  net count_reg[19]
    gate out_pad_25um[19] term A end
    gate I6.I4.I2 term Q2Z end
  end
  net count_reg[18]
    gate out_pad_25um[18] term A end
    gate I6.I4.I2 term QZ end
  end
  net count_reg[17]
    gate out_pad_25um[17] term A end
    gate I6.I5.I2 term Q2Z end
  end
  net count_reg[16]
    gate out_pad_25um[16] term A end
    gate I6.I5.I2 term QZ end
  end
  net count_reg[15]
    gate out_pad_25um[15] term A end
    gate I5.I6.I2 term Q2Z end
  end
  net count_reg[14]
    gate out_pad_25um[14] term A end
    gate I5.I6.I2 term QZ end
  end
  net count_reg[13]
    gate out_pad_25um[13] term A end
    gate I5.I7.I2 term Q2Z end
  end
  net count_reg[12]
    gate out_pad_25um[12] term A end
    gate I5.I7.I2 term QZ end
  end
  net count_reg[11]
    gate out_pad_25um[11] term A end
    gate I5.I8.I2 term Q2Z end
  end
  net count_reg[10]
    gate out_pad_25um[10] term A end
    gate I5.I8.I2 term QZ end
  end
  net count_reg[9]
    gate out_pad_25um[9] term A end
    gate I5.I9.I2 term Q2Z end
  end
  net count_reg[8]
    gate out_pad_25um[8] term A end
    gate I5.I9.I2 term QZ end
  end
  net count_reg[7]
    gate out_pad_25um[7] term A end
    gate I5.I2.I2 term Q2Z end
  end
  net count_reg[6]
    gate out_pad_25um[6] term A end
    gate I5.I2.I2 term QZ end
  end
  net count_reg[5]
    gate out_pad_25um[5] term A end
    gate I5.I3.I2 term Q2Z end
  end
  net count_reg[4]
    gate out_pad_25um[4] term A end
    gate I5.I3.I2 term QZ end
  end
  net count_reg[3]
    gate out_pad_25um[3] term A end
    gate I5.I4.I2 term Q2Z end
  end
  net count_reg[2]
    gate out_pad_25um[2] term A end
    gate I5.I4.I2 term QZ end
  end
  net count_reg[1]
    gate out_pad_25um[1] term A end
    gate I5.I5.I2 term Q2Z end
  end
  net count_reg[0]
    gate out_pad_25um[0] term A end
    gate I5.I5.I2 term QZ end
  end
  net count_out[31] direction output
    gate out_pad_25um[31] term P end
  end
  net count_out[30] direction output
    gate out_pad_25um[30] term P end
  end
  net count_out[29] direction output
    gate out_pad_25um[29] term P end
  end
  net count_out[28] direction output
    gate out_pad_25um[28] term P end
  end
  net count_out[27] direction output
    gate out_pad_25um[27] term P end
  end
  net count_out[26] direction output
    gate out_pad_25um[26] term P end
  end
  net count_out[25] direction output
    gate out_pad_25um[25] term P end
  end
  net count_out[24] direction output
    gate out_pad_25um[24] term P end
  end
  net count_out[23] direction output
    gate out_pad_25um[23] term P end
  end
  net count_out[22] direction output
    gate out_pad_25um[22] term P end
  end
  net count_out[21] direction output
    gate out_pad_25um[21] term P end
  end
  net count_out[20] direction output
    gate out_pad_25um[20] term P end
  end
  net count_out[19] direction output
    gate out_pad_25um[19] term P end
  end
  net count_out[18] direction output
    gate out_pad_25um[18] term P end
  end
  net count_out[17] direction output
    gate out_pad_25um[17] term P end
  end
  net count_out[16] direction output
    gate out_pad_25um[16] term P end
  end
  net count_out[15] direction output
    gate out_pad_25um[15] term P end
  end
  net count_out[14] direction output
    gate out_pad_25um[14] term P end
  end
  net count_out[13] direction output
    gate out_pad_25um[13] term P end
  end
  net count_out[12] direction output
    gate out_pad_25um[12] term P end
  end
  net count_out[11] direction output
    gate out_pad_25um[11] term P end
  end
  net count_out[10] direction output
    gate out_pad_25um[10] term P end
  end
  net count_out[9] direction output
    gate out_pad_25um[9] term P end
  end
  net count_out[8] direction output
    gate out_pad_25um[8] term P end
  end
  net count_out[7] direction output
    gate out_pad_25um[7] term P end
  end
  net count_out[6] direction output
    gate out_pad_25um[6] term P end
  end
  net count_out[5] direction output
    gate out_pad_25um[5] term P end
  end
  net count_out[4] direction output
    gate out_pad_25um[4] term P end
  end
  net count_out[3] direction output
    gate out_pad_25um[3] term P end
  end
  net count_out[2] direction output
    gate out_pad_25um[2] term P end
  end
  net count_out[1] direction output
    gate out_pad_25um[1] term P end
  end
  net count_out[0] direction output
    gate out_pad_25um[0] term P end
  end
  net .I5.I2.I2-AZ direction output
    gate I5.I2.I2 term AZ end
  end
  net .I5.I2.I2-OZ direction output
    gate I5.I2.I2 term OZ end
  end
  net .I5.I2.I2-NZ direction output
    gate I5.I2.I2 term NZ end
  end
  net .I5.I2.I2-FZ direction output
    gate I5.I2.I2 term FZ end
  end
  net .I5.I3.I2-AZ direction output
    gate I5.I3.I2 term AZ end
  end
  net .I5.I3.I2-OZ direction output
    gate I5.I3.I2 term OZ end
  end
  net .I5.I3.I2-NZ direction output
    gate I5.I3.I2 term NZ end
  end
  net .I5.I3.I2-FZ direction output
    gate I5.I3.I2 term FZ end
  end
  net .I5.I4.I2-AZ direction output
    gate I5.I4.I2 term AZ end
  end
  net .I5.I4.I2-OZ direction output
    gate I5.I4.I2 term OZ end
  end
  net .I5.I4.I2-NZ direction output
    gate I5.I4.I2 term NZ end
  end
  net .I5.I4.I2-FZ direction output
    gate I5.I4.I2 term FZ end
  end
  net .I5.I5.I2-AZ direction output
    gate I5.I5.I2 term AZ end
  end
  net .I5.I5.I2-OZ direction output
    gate I5.I5.I2 term OZ end
  end
  net .I5.I5.I2-NZ direction output
    gate I5.I5.I2 term NZ end
  end
  net .I5.I5.I2-FZ direction output
    gate I5.I5.I2 term FZ end
  end
  net .I5.I6.I2-AZ direction output
    gate I5.I6.I2 term AZ end
  end
  net .I5.I6.I2-OZ direction output
    gate I5.I6.I2 term OZ end
  end
  net .I5.I6.I2-NZ direction output
    gate I5.I6.I2 term NZ end
  end
  net .I5.I6.I2-FZ direction output
    gate I5.I6.I2 term FZ end
  end
  net .I5.I7.I2-AZ direction output
    gate I5.I7.I2 term AZ end
  end
  net .I5.I7.I2-OZ direction output
    gate I5.I7.I2 term OZ end
  end
  net .I5.I7.I2-NZ direction output
    gate I5.I7.I2 term NZ end
  end
  net .I5.I7.I2-FZ direction output
    gate I5.I7.I2 term FZ end
  end
  net .I5.I8.I2-AZ direction output
    gate I5.I8.I2 term AZ end
  end
  net .I5.I8.I2-OZ direction output
    gate I5.I8.I2 term OZ end
  end
  net .I5.I8.I2-NZ direction output
    gate I5.I8.I2 term NZ end
  end
  net .I5.I8.I2-FZ direction output
    gate I5.I8.I2 term FZ end
  end
  net .I5.I9.I2-AZ direction output
    gate I5.I9.I2 term AZ end
  end
  net .I5.I9.I2-OZ direction output
    gate I5.I9.I2 term OZ end
  end
  net .I5.I9.I2-NZ direction output
    gate I5.I9.I2 term NZ end
  end
  net .I5.I9.I2-FZ direction output
    gate I5.I9.I2 term FZ end
  end
  net .I6.I2.I2-AZ direction output
    gate I6.I2.I2 term AZ end
  end
  net .I6.I2.I2-OZ direction output
    gate I6.I2.I2 term OZ end
  end
  net .I6.I2.I2-NZ direction output
    gate I6.I2.I2 term NZ end
  end
  net .I6.I2.I2-FZ direction output
    gate I6.I2.I2 term FZ end
  end
  net .I6.I3.I2-AZ direction output
    gate I6.I3.I2 term AZ end
  end