example_en_32bit_a.spd

VHDL examples for counter design, use QuickLogic eclips

; Time: Thu Aug 14 11:16:41 2003
; Status: Logic Optimizer complete
; Options for placer
; placer.Seed = 42
; placer.Mode = Quality
; placer.Lambda = 0.300000
; placer.Level = 1
; placer.FastAnnealer = 2
; Time: Thu Aug 14 11:16:41 2003
; Status: Placer begin...
; Time: Thu Aug 14 11:16:41 2003
; Status: global placer begin...
Debug: WindowBasedPlacer:  62 blocks with window constraints assigned
Debug: Initializing Ad Module
; Time: Thu Aug 14 11:16:41 2003
; Status: Initializing AD with constraints ...
; Time: Thu Aug 14 11:16:41 2003
; Status: FastPlacer running...
Debug: level=0  ,   bbCost=1095.000000 
Debug: level=1  ,   bbCost=1146.000000 
Debug: level=2  ,   bbCost=1132.000000 
; Time: Thu Aug 14 11:16:43 2003
; Status: FastPlacer: clock assignment routines...
currentbCost = 644.000000
IntSearchTemp: temp= 10 costFactor= 0.118012 
Debug: Temp 22.500000, rate 1.000000, cost 644, sigma 0.100000
Debug: Temp 0.136642, rate 0.067027, cost 533, sigma 0.100000
; Time: Thu Aug 14 11:16:47 2003
; Status: clock assignment routines complete
; Time: Thu Aug 14 11:16:47 2003
; Status: FastPlacer finished
Debug: Closing Ad-Module
; Time: Thu Aug 14 11:16:47 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:47 2003
; Status: Post-placement optimization.
; Time: Thu Aug 14 11:16:47 2003
; Status: placement buffering starts.
; Time: Thu Aug 14 11:16:47 2003
; Status: Placement buffering complete -- 15 buffers inserted.
Debug: WindowBasedPlacer:  62 blocks with window constraints assigned
Debug: Initializing Ad Module
; Time: Thu Aug 14 11:16:47 2003
; Status: Initializing AD with constraints ...
Debug: Closing Ad-Module
; Time: Thu Aug 14 11:16:48 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:48 2003
; Status: global placer complete
; Time: Thu Aug 14 11:16:48 2003
; Status: detail placer begin...
Debug: WindowBasedPlacer:  62 blocks with window constraints assigned
Debug: Initializing Ad Module
; Time: Thu Aug 14 11:16:48 2003
; Status: Initializing AD with constraints ...
; Time: Thu Aug 14 11:16:48 2003
; Status: Finding initial temperature...
currentbCost = 612.000000
IntSearchTemp: temp= 10 costFactor= 0.000000 
IntSearchTemp: temp= 14 costFactor= 0.151961 
; Time: Thu Aug 14 11:16:48 2003
; Status: Cycle loop begin...
Debug: Temp 19.600000, rate 1.000000, Beta 0, cost 533, bbCost 665.000000, tdCost 11.051448, Cost 1352.536708, sigma 0.024821
Debug: Temp 0.000000, rate 0.031910, Beta 26.1565, cost 512, bbCost 591.000000, tdCost 7.452613, Cost 785.934435, sigma 0.061048
; Time: Thu Aug 14 11:16:53 2003
; Status: Cycle loop with 251425 attempted moves complete
Debug: Closing Ad-Module
; Time: Thu Aug 14 11:16:53 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:53 2003
; Status: detail placer complete
; Time: Thu Aug 14 11:16:53 2003
; Status: Placer complete
; Time: Thu Aug 14 11:16:53 2003
; Status: Post-placement optimization.
; Time: Thu Aug 14 11:16:53 2003
; Status: Auto buffering starts.
; Time: Thu Aug 14 11:16:53 2003
; Result: ;Summary: Logic cell utilization: 1
; Time: Thu Aug 14 11:16:53 2003
; Result: ; Summary: IO control cells: 0 of 16
; Time: Thu Aug 14 11:16:53 2003
; Result: ; Summary: Clock-only cells: 2 of 9
; Time: Thu Aug 14 11:16:53 2003
; Result: ; Summary: Bi-directional cells: 33 of 310
; Time: Thu Aug 14 11:16:53 2003
; Status: Auto buffering complete -- 4 buffers inserted.
; Time: Thu Aug 14 11:16:53 2003
; Status: Global router begin...
; Time: Thu Aug 14 11:16:53 2003
; Status: R2: initializing...
; Time: Thu Aug 14 11:16:54 2003
; Status: Fragment-Level Netlister begin...
; Time: Thu Aug 14 11:16:54 2003
; Status: Fragment-Level Netlister complete
; Time: Thu Aug 14 11:16:54 2003
; Status: Initializing AD with constraints ...
; Time: Thu Aug 14 11:16:54 2003
; Status: R2: beginning initial cycle
; Time: Thu Aug 14 11:16:55 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:55 2003
; Status: R2 Global router complete.
; Time: Thu Aug 14 11:16:55 2003
; Status: Layout Based optimization.
; Time: Thu Aug 14 11:16:55 2003
; Status: Initializing AD with constraints ...
; Time: Thu Aug 14 11:16:55 2003
; Status: Timing driven calculations begin...
; Time: Thu Aug 14 11:16:55 2003
; Status: Timing driven calculations end...
; Time: Thu Aug 14 11:16:56 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:56 2003
; Status: Post Layout buffering complete -- 2 buffers inserted.
; Time: Thu Aug 14 11:16:56 2003
; Status: Fixing bypass muxes starts.
; Time: Thu Aug 14 11:16:56 2003
; Status: Fixing bypass muxes--0 bypass muxes, 0 swaps.
; Time: Thu Aug 14 11:16:56 2003
; Status: Fragment-Level Netlister begin...
; Time: Thu Aug 14 11:16:56 2003
; Status: Fragment-Level Netlister complete
; Time: Thu Aug 14 11:16:56 2003
; Status: Fragment simulator begins ...
; Time: Thu Aug 14 11:16:57 2003
; Status: Fragment simulator ends successfully.
; Options for router
; router.MinCycles = 5
; router.MaxCycles = 512
; router.Seed = 42
; router.LoopCnt = 5
; router.MaxHidriveFanouts = 20
; router.CongestionTable = 0
; router.RouteMode = 0
; router.PureMagic = 0
; router.NetMagic = 0
; router.UnusedIO = 0
; Time: Thu Aug 14 11:16:57 2003
; Status: R2 router begin...
; Time: Thu Aug 14 11:16:57 2003
; Status: R2: routing clock nets
; Time: Thu Aug 14 11:16:57 2003
; Status: R2: routing supply nets
; Time: Thu Aug 14 11:16:57 2003
; Status: R2: initializing...
; Time: Thu Aug 14 11:16:58 2003
; Status: Fragment-Level Netlister begin...
; Time: Thu Aug 14 11:16:58 2003
; Status: Fragment-Level Netlister complete
; Time: Thu Aug 14 11:16:58 2003
; Status: Initializing AD with constraints ...
; Time: Thu Aug 14 11:16:58 2003
; Status: R2: routing low skew nets
; Time: Thu Aug 14 11:16:58 2003
; Status: R2: routing conventional nets...
; Time: Thu Aug 14 11:16:58 2003
; Status: R2: beginning initial cycle
Debug: cycle= 0: cong= 0  over= 0  histoc= 0
Debug: cycle= 0: overconstraints= 12
; Time: Thu Aug 14 11:16:58 2003
; Status: Timing driven calculations begin...
; Time: Thu Aug 14 11:16:58 2003
; Status: Timing driven calculations end...
Debug: cycle= 1: cong= 0  over= 0.105  histoc= 0
Debug: cycle= 1: overconstraints= 0
; Time: Thu Aug 14 11:16:58 2003
; Status: R2: detail routing...
; Time: Thu Aug 14 11:16:58 2003
; Status: R2: writeback...
; Time: Thu Aug 14 11:16:59 2003
; Status: AD Close...
; Time: Thu Aug 14 11:16:59 2003
; Status: R2 router complete.
; Options for delay modeler
; delay modeler.Mode = Commercial
; delay modeler.Corner = Worst
; delay modeler.OutPadCap = 30.000000
; delay modeler.SpeedGrade = 8
; delay modeler.LowPower = FALSE
; delay modeler.CustomVccBest = 1.800000
; delay modeler.CustomVccNominal = 1.800000
; delay modeler.CustomVccWorst = 1.800000
; delay modeler.CustomVccLPBest = 3.600000
; delay modeler.CustomVccLPNominal = 3.300000
; delay modeler.CustomVccLPWorst = 3.000000
; delay modeler.CustomTempBest = 25.000000
; delay modeler.CustomTempNominal = 25.000000
; delay modeler.CustomTempWorst = 25.000000
; Time: Thu Aug 14 11:16:59 2003
; Status: Delay Simulator begin...
; Time: Thu Aug 14 11:16:59 2003
; Status: Delay Simulator complete
; Options for back annotation
; Time: Thu Aug 14 11:16:59 2003
; Status: Verilog back annotation begin...
; Time: Thu Aug 14 11:16:59 2003
; Status: Verilog netlist begin...
; Time: Thu Aug 14 11:16:59 2003
; Status: Verilog back annotation in progress...
; Time: Thu Aug 14 11:17:01 2003
; Status: Verilog netlist complete
; Time: Thu Aug 14 11:17:01 2003
; Status: SDF back annotation begin...
; Time: Thu Aug 14 11:17:02 2003
; Status: SDF back annotation complete
; Time: Thu Aug 14 11:17:02 2003
; Status: Verilog back annotation complete
; Time: Thu Aug 14 11:17:02 2003
; Status: Back annotation begin...
; Time: Thu Aug 14 11:17:02 2003
; Status: Back annotation complete
; Time: Thu Aug 14 11:17:04 2003
; Status: Report file example_en_32bit_a.rpt created.