example_en_32bit_a.v

VHDL examples for counter design, use QuickLogic eclips

/* Verilog Model Created from SCS Schematic example_en_32bit_a.sch 
   Aug 18, 2004 18:06 */

/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
	`ifdef synthesis
	`else
	`define synthesis
	`endif
`endif

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_en_32bit_a( clear_in , clk_in, enable_in, count_out );
input clear_in;
input clk_in /* synthesis syn_isclock=1 */;
//exemplar attribute clk_in syn_isclock true
 output [31:0] count_out;
input enable_in;
// exemplar attribute example_en_32bit_a dont_touch true 
parameter syn_macro = 1;
wire [31:0] count_reg;
wire [31:0] count;
wire enable;
wire clear;
wire clk;

counter_en_32bit_a I9 ( .clear(clear), .clk(clk), .count({ count[31:0] }),
                     .enable(enable) );
outpad_25um \out_pad_25um[31]  ( .A(count_reg[31]), .P(count_out[31]) );
outpad_25um \out_pad_25um[30]  ( .A(count_reg[30]), .P(count_out[30]) );
outpad_25um \out_pad_25um[29]  ( .A(count_reg[29]), .P(count_out[29]) );
outpad_25um \out_pad_25um[28]  ( .A(count_reg[28]), .P(count_out[28]) );
outpad_25um \out_pad_25um[27]  ( .A(count_reg[27]), .P(count_out[27]) );
outpad_25um \out_pad_25um[26]  ( .A(count_reg[26]), .P(count_out[26]) );
outpad_25um \out_pad_25um[25]  ( .A(count_reg[25]), .P(count_out[25]) );
outpad_25um \out_pad_25um[24]  ( .A(count_reg[24]), .P(count_out[24]) );
outpad_25um \out_pad_25um[23]  ( .A(count_reg[23]), .P(count_out[23]) );
outpad_25um \out_pad_25um[22]  ( .A(count_reg[22]), .P(count_out[22]) );
outpad_25um \out_pad_25um[21]  ( .A(count_reg[21]), .P(count_out[21]) );
outpad_25um \out_pad_25um[20]  ( .A(count_reg[20]), .P(count_out[20]) );
outpad_25um \out_pad_25um[19]  ( .A(count_reg[19]), .P(count_out[19]) );
outpad_25um \out_pad_25um[18]  ( .A(count_reg[18]), .P(count_out[18]) );
outpad_25um \out_pad_25um[17]  ( .A(count_reg[17]), .P(count_out[17]) );
outpad_25um \out_pad_25um[16]  ( .A(count_reg[16]), .P(count_out[16]) );
outpad_25um \out_pad_25um[15]  ( .A(count_reg[15]), .P(count_out[15]) );
outpad_25um \out_pad_25um[14]  ( .A(count_reg[14]), .P(count_out[14]) );
outpad_25um \out_pad_25um[13]  ( .A(count_reg[13]), .P(count_out[13]) );
outpad_25um \out_pad_25um[12]  ( .A(count_reg[12]), .P(count_out[12]) );
outpad_25um \out_pad_25um[11]  ( .A(count_reg[11]), .P(count_out[11]) );
outpad_25um \out_pad_25um[10]  ( .A(count_reg[10]), .P(count_out[10]) );
outpad_25um \out_pad_25um[9]  ( .A(count_reg[9]), .P(count_out[9]) );
outpad_25um \out_pad_25um[8]  ( .A(count_reg[8]), .P(count_out[8]) );
outpad_25um \out_pad_25um[7]  ( .A(count_reg[7]), .P(count_out[7]) );
outpad_25um \out_pad_25um[6]  ( .A(count_reg[6]), .P(count_out[6]) );
outpad_25um \out_pad_25um[5]  ( .A(count_reg[5]), .P(count_out[5]) );
outpad_25um \out_pad_25um[4]  ( .A(count_reg[4]), .P(count_out[4]) );
outpad_25um \out_pad_25um[3]  ( .A(count_reg[3]), .P(count_out[3]) );
outpad_25um \out_pad_25um[2]  ( .A(count_reg[2]), .P(count_out[2]) );
outpad_25um \out_pad_25um[1]  ( .A(count_reg[1]), .P(count_out[1]) );
outpad_25um \out_pad_25um[0]  ( .A(count_reg[0]), .P(count_out[0]) );
inpad_25um I2 ( .P(enable_in), .Q(enable) );
ckpad_25um I3 ( .P(clk_in), .Q(clk) );
ckpad_25um I4 ( .P(clear_in), .Q(clear) );
rg16_25um I5 ( .CLK(clk), .D({ count[15:0] }), .Q({ count_reg[15:0] }) );
rg16_25um I6 ( .CLK(clk), .D({ count[31:16] }), .Q({ count_reg[31:16] }) );

endmodule // example_en_32bit_a


`ifdef counter_en_32bit_a
`else
`define counter_en_32bit_a
module counter_en_32bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [31:0] count;
input enable;
// exemplar attribute counter_en_32bit_a dont_touch true 
parameter syn_macro = 1;
wire enable32bit_h_a;
wire enable_32bit1_a;
supply0 gnd;

counter_en_16bit_a I15 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
                      .enable(enable) );
counter_en_16bit_a I16 ( .clear(clear), .clk(clk), .count({ count[31:16] }),
                      .enable(enable32bit_h_a) );
super_logic I1 ( .A1(count[6]), .A2(gnd), .A3(count[5]), .A4(gnd), .A5(count[4]),
              .A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd), .D1(gnd),
              .D2(gnd), .E1(count[2]), .E2(gnd), .F1(count[0]), .F2(gnd),
              .F3(enable_32bit1_a), .F4(gnd), .F5(enable), .F6(gnd), .MP(gnd),
              .MS(gnd), .NP(count[1]), .NS(gnd), .OP(count[3]), .OS(gnd),
              .OZ(enable32bit_h_a), .PP(gnd), .PS(gnd), .QC(gnd), .QR(gnd),
              .QS(gnd), .AZ(), .FZ(), .NZ(), .Q2Z(), .QZ() );
super_logic I2 ( .A1(count[15]), .A2(gnd), .A3(count[14]), .A4(gnd),
              .A5(count[13]), .A6(gnd), .B1(gnd), .B2(gnd), .C1(gnd), .C2(gnd),
              .D1(gnd), .D2(gnd), .E1(count[11]), .E2(gnd), .F1(count[9]),
              .F2(gnd), .F3(count[8]), .F4(gnd), .F5(count[7]), .F6(gnd),
              .MP(gnd), .MS(gnd), .NP(count[10]), .NS(gnd), .OP(count[12]),
              .OS(gnd), .OZ(enable_32bit1_a), .PP(gnd), .PS(gnd), .QC(gnd),
              .QR(gnd), .QS(gnd), .AZ(), .FZ(), .NZ(), .Q2Z(), .QZ() );

endmodule // counter_en_32bit_a

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
// exemplar attribute outpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
// exemplar attribute inpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P /* synthesis syn_isclock=1 */;
//exemplar attribute P syn_isclock true
output Q;
// exemplar attribute ckpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
 input [15:0] D;
 output [15:0] Q;
// exemplar attribute rg16_25um dont_touch true 
parameter syn_macro = 1;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef counter_en_16bit_a
`else
`define counter_en_16bit_a
module counter_en_16bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [15:0] count;
input enable;
// exemplar attribute counter_en_16bit_a dont_touch true 
parameter syn_macro = 1;
wire enable_8bit_h;

counter_en_8bit_ii_a I6 ( .clear(enable_8bit_h), .clk(clk),
                       .count({ count[15:8] }), .enable(clear) );
counter_en_8bit_i_a I7 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
                      .en_8bit_a(enable_8bit_h), .enable(enable) );

endmodule // counter_en_16bit_a

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC /* synthesis syn_isclock=1 */;
//exemplar attribute QC syn_isclock true
input QR, QS;
output QZ;
// exemplar attribute super_logic dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute eio_cell noopt true 
 wire EQMUX_Z, OQMUX_Z;  
 reg EQZ, OQQ, IQQ;  
 assign #1 EQMUX_Z = ESEL ? IE : EQZ;  
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ;  
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz;  
 assign #1 IZ = IP;  
 
`ifdef synthesis  
  always @ (posedge IQC or posedge IQR)  
    if (IQR) 
      #1 EQZ = 1'b0; 
    else if (EQE)