example_en_32bit_a.chp

VHDL examples for counter design, use QuickLogic eclips

    term RD[12] port RD12 end
    term RD[11] port RD11 end
    term RD[10] port RD10 end
    term RD[9] port RD9 end
    term RD[8] port RD8 end
    term RD[7] port RD7 end
    term RD[6] port RD6 end
    term RD[5] port RD5 end
    term RD[4] port RD4 end
    term RD[3] port RD3 end
    term RD[2] port RD2 end
    term RD[1] port RD1 end
    term RD[0] port RD0 end
    term GND port WA9 port WA8 port WA7 port RA9 port RA8 port RA7 port MODE1 port MODE0 end
    term VCC end
  end
  gate ECU cell QMATH
    term SIGN2 port SIGN2 end
    term SIGN1 port SIGN1 end
    term RESET port RESET end
    term CLK port CLK end
    term A[15] port A15 end
    term A[14] port A14 end
    term A[13] port A13 end
    term A[12] port A12 end
    term A[11] port A11 end
    term A[10] port A10 end
    term A[9] port A9 end
    term A[8] port A8 end
    term A[7] port A7 end
    term A[6] port A6 end
    term A[5] port A5 end
    term A[4] port A4 end
    term A[3] port A3 end
    term A[2] port A2 end
    term A[1] port A1 end
    term A[0] port A0 end
    term B[15] port B15 end
    term B[14] port B14 end
    term B[13] port B13 end
    term B[12] port B12 end
    term B[11] port B11 end
    term B[10] port B10 end
    term B[9] port B9 end
    term B[8] port B8 end
    term B[7] port B7 end
    term B[6] port B6 end
    term B[5] port B5 end
    term B[4] port B4 end
    term B[3] port B3 end
    term B[2] port B2 end
    term B[1] port B1 end
    term B[0] port B0 end
    term S3 port S3 end
    term S2 port S2 end
    term S1 port S1 end
    term CIN port CIN end
    term Q[16] port OUT16 end
    term Q[15] port OUT15 end
    term Q[14] port OUT14 end
    term Q[13] port OUT13 end
    term Q[12] port OUT12 end
    term Q[11] port OUT11 end
    term Q[10] port OUT10 end
    term Q[9] port OUT9 end
    term Q[8] port OUT8 end
    term Q[7] port OUT7 end
    term Q[6] port OUT6 end
    term Q[5] port OUT5 end
    term Q[4] port OUT4 end
    term Q[3] port OUT3 end
    term Q[2] port OUT2 end
    term Q[1] port OUT1 end
    term Q[0] port OUT0 end
    term GND end
    term VCC end
  end
  gate PLL_TOP cell PLL
    term S4 port S4 end
    term S3 port S3 end
    term S2 port S2 end
    term S1 port S1 end
    term LOCK_DETECTn port LD end
    term PLLCLK_NET port PLLCK end
    term CLKPAD_OUT port PLLOUT end
    term PLL_RESET port PLLRST end
    term PLLCLK_IN port PLLIN end
    term GND end
    term VCC end
  end
  gate PLL_OUTPAD_25UM cell PLLOUTPAD
    term S port SEL end
    term P port IP end
    term A port IZ end
    term GND end
    term VCC end
  end
  gate PLL_RSTPAD_25UM cell PLLRSTPAD
    term Q port IZ end
    term P port IP end
    term GND end
    term VCC end
  end
  gate PLL_CLKPAD_25UM cell CLOCK
    term O port OP end
    term Q port IC end
    term P port IP end
    term GND end
    term VCC end
  end
  gate F1BUFF cell LOGIC
    term GND port F6 port F4 port F2 end
    term VCC port F5 port F3 end
    term Z port FZ end
    term A port F1 end
  end
  gate CLK2HWCLK cell HWCLOCK
    term P port IP end
    term Q port IC end
    term VCC end
    term GND end
  end
end
logical example_en_32bit_a
  gates 74
  nets 290
  gate I2 master INPAD_25UM end
  gate I3 master CLK2HWCLK end
  gate I4 master CKPAD_25UM end
  gate I5.I2.I2 master SUPER_LOGIC end
  gate I5.I3.I2 master SUPER_LOGIC end
  gate I5.I4.I2 master SUPER_LOGIC end
  gate I5.I5.I2 master SUPER_LOGIC end
  gate I5.I6.I2 master SUPER_LOGIC end
  gate I5.I7.I2 master SUPER_LOGIC end
  gate I5.I8.I2 master SUPER_LOGIC end
  gate I5.I9.I2 master SUPER_LOGIC end
  gate I6.I2.I2 master SUPER_LOGIC end
  gate I6.I3.I2 master SUPER_LOGIC end
  gate I6.I4.I2 master SUPER_LOGIC end
  gate I6.I5.I2 master SUPER_LOGIC end
  gate I6.I6.I2 master SUPER_LOGIC end
  gate I6.I7.I2 master SUPER_LOGIC end
  gate I6.I8.I2 master SUPER_LOGIC end
  gate I6.I9.I2 master SUPER_LOGIC end
  gate I9.I1 master SUPER_LOGIC end
  gate I9.I2 master SUPER_LOGIC end
  gate I9.I15.I6.I4.I1 master SUPER_LOGIC end
  gate I9.I15.I6.I4.I2 master SUPER_LOGIC end
  gate I9.I15.I6.I5.I1 master SUPER_LOGIC end
  gate I9.I15.I6.I5.I2 master SUPER_LOGIC end
  gate I9.I15.I7.I1 master SUPER_LOGIC end
  gate I9.I15.I7.I2 master SUPER_LOGIC end
  gate I9.I15.I7.I8.I1 master SUPER_LOGIC end
  gate I9.I15.I7.I8.I2 master SUPER_LOGIC end
  gate I9.I15.I7.I9.I1 master SUPER_LOGIC end
  gate I9.I15.I7.I9.I2 master SUPER_LOGIC end
  gate I9.I16.I6.I4.I1 master SUPER_LOGIC end
  gate I9.I16.I6.I4.I2 master SUPER_LOGIC end
  gate I9.I16.I6.I5.I1 master SUPER_LOGIC end
  gate I9.I16.I6.I5.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I8.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I8.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I9.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I9.I2 master SUPER_LOGIC end
  gate out_pad_25um[31] master OUTPAD_25UM end
  gate out_pad_25um[30] master OUTPAD_25UM end
  gate out_pad_25um[29] master OUTPAD_25UM end
  gate out_pad_25um[28] master OUTPAD_25UM end
  gate out_pad_25um[27] master OUTPAD_25UM end
  gate out_pad_25um[26] master OUTPAD_25UM end
  gate out_pad_25um[25] master OUTPAD_25UM end
  gate out_pad_25um[24] master OUTPAD_25UM end
  gate out_pad_25um[23] master OUTPAD_25UM end
  gate out_pad_25um[22] master OUTPAD_25UM end
  gate out_pad_25um[21] master OUTPAD_25UM end
  gate out_pad_25um[20] master OUTPAD_25UM end
  gate out_pad_25um[19] master OUTPAD_25UM end
  gate out_pad_25um[18] master OUTPAD_25UM end
  gate out_pad_25um[17] master OUTPAD_25UM end
  gate out_pad_25um[16] master OUTPAD_25UM end
  gate out_pad_25um[15] master OUTPAD_25UM end
  gate out_pad_25um[14] master OUTPAD_25UM end
  gate out_pad_25um[13] master OUTPAD_25UM end
  gate out_pad_25um[12] master OUTPAD_25UM end
  gate out_pad_25um[11] master OUTPAD_25UM end
  gate out_pad_25um[10] master OUTPAD_25UM end
  gate out_pad_25um[9] master OUTPAD_25UM end
  gate out_pad_25um[8] master OUTPAD_25UM end
  gate out_pad_25um[7] master OUTPAD_25UM end
  gate out_pad_25um[6] master OUTPAD_25UM end
  gate out_pad_25um[5] master OUTPAD_25UM end
  gate out_pad_25um[4] master OUTPAD_25UM end
  gate out_pad_25um[3] master OUTPAD_25UM end
  gate out_pad_25um[2] master OUTPAD_25UM end
  gate out_pad_25um[1] master OUTPAD_25UM end
  gate out_pad_25um[0] master OUTPAD_25UM end
  gate clear_buf1 master F1BUFF end
  net clk clock 1
    gate I9.I16.I6.I4.I2 term DCLK end
    gate I9.I16.I6.I4.I1 term DCLK end
    gate I9.I16.I6.I5.I2 term DCLK end
    gate I9.I16.I6.I5.I1 term DCLK end
    gate I9.I16.I7.I8.I2 term DCLK end
    gate I9.I16.I7.I8.I1 term DCLK end
    gate I9.I16.I7.I9.I2 term DCLK end
    gate I9.I16.I7.I9.I1 term DCLK end
    gate I9.I15.I6.I4.I2 term DCLK end
    gate I9.I15.I6.I4.I1 term DCLK end
    gate I9.I15.I6.I5.I2 term DCLK end
    gate I9.I15.I6.I5.I1 term DCLK end
    gate I9.I15.I7.I8.I2 term DCLK end
    gate I9.I15.I7.I8.I1 term DCLK end
    gate I9.I15.I7.I9.I2 term DCLK end
    gate I9.I15.I7.I9.I1 term DCLK end
    gate I5.I9.I2 term DCLK end
    gate I5.I8.I2 term DCLK end
    gate I5.I7.I2 term DCLK end
    gate I5.I6.I2 term DCLK end
    gate I5.I5.I2 term DCLK end
    gate I5.I4.I2 term DCLK end
    gate I5.I3.I2 term DCLK end
    gate I5.I2.I2 term DCLK end
    gate I6.I9.I2 term DCLK end
    gate I6.I8.I2 term DCLK end
    gate I6.I7.I2 term DCLK end
    gate I6.I6.I2 term DCLK end
    gate I6.I5.I2 term DCLK end
    gate I6.I4.I2 term DCLK end
    gate I6.I3.I2 term DCLK end
    gate I6.I2.I2 term DCLK end
    gate I3 term Q end
  end
  net clear clock 3
    gate clear_buf1 term A end
    gate I9.I15.I7.I9.I1 term QR end
    gate I9.I15.I7.I9.I2 term QR end
    gate I9.I15.I7.I8.I1 term QR end
    gate I9.I15.I7.I8.I2 term QR end
    gate I9.I15.I6.I5.I1 term F1 end
    gate I9.I16.I7.I9.I1 term QR end
    gate I9.I16.I7.I9.I2 term QR end
    gate I9.I16.I7.I8.I1 term QR end
    gate I9.I16.I7.I8.I2 term QR end
    gate I9.I16.I6.I5.I1 term F1 end
    gate I4 term Q end
  end
  net enable
    gate I9.I15.I7.I8.I1 term F1 end
    gate I9.I15.I7.I8.I2 term MP end
    gate I9.I15.I7.I8.I2 term D1 end
    gate I9.I15.I7.I8.I2 term E2 end
    gate I9.I15.I7.I1 term F5 end
    gate I9.I1 term F5 end
    gate I2 term Q end
  end
  net clk_in direction INPUT
    gate I3 term P end
  end
  net clear_in direction INPUT
    gate I4 term P end
  end
  net enable_in direction INPUT
    gate I2 term P end
  end
  net count[31]
    gate I9.I16.I6.I4.I1 term A5 end
    gate I9.I16.I6.I4.I2 term C2 end
    gate I9.I16.I6.I4.I2 term B1 end
    gate I9.I16.I6.I4.I2 term QZ end
    gate I6.I6.I2 term PS end
  end
  net count[30]
    gate I9.I16.I6.I4.I1 term Q2Z end
    gate I9.I16.I6.I4.I1 term E2 end
    gate I9.I16.I6.I4.I1 term D1 end
    gate I9.I16.I6.I4.I2 term F1 end
    gate I6.I6.I2 term E1 end
  end
  net count[29]
    gate I9.I16.I6.I4.I1 term QZ end
    gate I9.I16.I6.I4.I1 term C1 end
    gate I9.I16.I6.I4.I1 term B2 end
    gate I9.I16.I6.I4.I1 term MS end
    gate I9.I16.I6.I4.I2 term F3 end
    gate I9.I16.I6.I4.I1 term F1 end
    gate I6.I7.I2 term PS end
  end
  net count[28]
    gate I9.I16.I6.I4.I2 term NS end
    gate I9.I16.I6.I4.I1 term F3 end
    gate I9.I16.I6.I4.I2 term F5 end
    gate I9.I16.I6.I4.I2 term E1 end
    gate I9.I16.I6.I4.I2 term D2 end
    gate I9.I16.I6.I4.I2 term Q2Z end
    gate I6.I7.I2 term E1 end
  end
  net count[27]
    gate I9.I16.I6.I5.I1 term A5 end
    gate I9.I16.I6.I5.I2 term C2 end
    gate I9.I16.I6.I5.I2 term B1 end
    gate I9.I16.I6.I5.I2 term QZ end
    gate I6.I8.I2 term PS end
  end
  net count[26]
    gate I9.I16.I6.I5.I1 term Q2Z end
    gate I9.I16.I6.I5.I1 term E2 end
    gate I9.I16.I6.I5.I1 term D1 end
    gate I9.I16.I6.I5.I2 term F1 end
    gate I6.I8.I2 term E1 end
  end
  net count[25]
    gate I9.I16.I6.I5.I1 term QZ end
    gate I9.I16.I6.I5.I1 term C1 end
    gate I9.I16.I6.I5.I1 term B2 end
    gate I9.I16.I6.I5.I1 term MS end
    gate I9.I16.I6.I5.I2 term F3 end
    gate I9.I16.I6.I5.I1 term NP end
    gate I6.I9.I2 term PS end
  end
  net count[24]
    gate I9.I16.I6.I5.I2 term NS end
    gate I9.I16.I6.I5.I1 term F3 end
    gate I9.I16.I6.I5.I2 term F5 end
    gate I9.I16.I6.I5.I2 term E1 end
    gate I9.I16.I6.I5.I2 term D2 end
    gate I9.I16.I6.I5.I2 term Q2Z end
    gate I6.I9.I2 term E1 end
  end
  net count[23]
    gate I9.I16.I7.I9.I1 term A5 end
    gate I9.I16.I7.I9.I2 term C2 end
    gate I9.I16.I7.I9.I2 term B1 end
    gate I9.I16.I7.I9.I2 term QZ end
    gate I9.I16.I7.I1 term F3 end
    gate I6.I2.I2 term PS end
  end
  net count[22]
    gate I9.I16.I7.I9.I1 term Q2Z end
    gate I9.I16.I7.I9.I1 term E2 end
    gate I9.I16.I7.I9.I1 term D1 end
    gate I9.I16.I7.I9.I2 term F1 end
    gate I9.I16.I7.I1 term F1 end
    gate I6.I2.I2 term E1 end
  end
  net count[21]
    gate I9.I16.I7.I9.I1 term QZ end
    gate I9.I16.I7.I9.I1 term C1 end
    gate I9.I16.I7.I9.I1 term B2 end
    gate I9.I16.I7.I9.I1 term MS end
    gate I9.I16.I7.I9.I2 term F3 end
    gate I9.I16.I7.I9.I1 term NP end
    gate I9.I16.I7.I2 term A5 end
    gate I6.I3.I2 term PS end
  end
  net count[20]
    gate I9.I16.I7.I9.I2 term NS end
    gate I9.I16.I7.I9.I1 term F3 end
    gate I9.I16.I7.I9.I2 term F5 end
    gate I9.I16.I7.I9.I2 term E1 end
    gate I9.I16.I7.I9.I2 term D2 end
    gate I9.I16.I7.I9.I2 term Q2Z end
    gate I9.I16.I7.I2 term A3 end
    gate I6.I3.I2 term E1 end
  end
  net count[19]
    gate I9.I16.I7.I8.I1 term A5 end
    gate I9.I16.I7.I8.I2 term C2 end
    gate I9.I16.I7.I8.I2 term B1 end
    gate I9.I16.I7.I8.I2 term QZ end
    gate I9.I16.I7.I2 term A1 end
    gate I6.I4.I2 term PS end
  end
  net count[18]
    gate I9.I16.I7.I8.I1 term Q2Z end
    gate I9.I16.I7.I8.I1 term E2 end
    gate I9.I16.I7.I8.I1 term D1 end
    gate I9.I16.I7.I8.I2 term F1 end
    gate I9.I16.I7.I1 term A5 end
    gate I6.I4.I2 term E1 end
  end
  net count[17]
    gate I9.I16.I7.I8.I1 term QZ end
    gate I9.I16.I7.I8.I1 term C1 end
    gate I9.I16.I7.I8.I1 term B2 end
    gate I9.I16.I7.I8.I1 term MS end
    gate I9.I16.I7.I8.I2 term F3 end
    gate I9.I16.I7.I8.I1 term NP end
    gate I9.I16.I7.I1 term A3 end
    gate I6.I5.I2 term PS end
  end
  net count[16]
    gate I9.I16.I7.I8.I2 term NS end
    gate I9.I16.I7.I8.I1 term F3 end
    gate I9.I16.I7.I8.I2 term F5 end
    gate I9.I16.I7.I8.I2 term E1 end
    gate I9.I16.I7.I8.I2 term D2 end
    gate I9.I16.I7.I8.I2 term Q2Z end
    gate I9.I16.I7.I1 term A1 end
    gate I6.I5.I2 term E1 end
  end
  net count[15]
    gate I9.I15.I6.I4.I1 term A5 end
    gate I9.I15.I6.I4.I2 term C2 end
    gate I9.I15.I6.I4.I2 term B1 end
    gate I9.I15.I6.I4.I2 term QZ end
    gate I9.I2 term A1 end
    gate I5.I6.I2 term PS end
  end
  net count[14]
    gate I9.I15.I6.I4.I1 term Q2Z end
    gate I9.I15.I6.I4.I1 term E2 end
    gate I9.I15.I6.I4.I1 term D1 end
    gate I9.I15.I6.I4.I2 term F1 end
    gate I9.I2 term A3 end
    gate I5.I6.I2 term E1 end
  end
  net count[13]
    gate I9.I15.I6.I4.I1 term QZ end
    gate I9.I15.I6.I4.I1 term C1 end
    gate I9.I15.I6.I4.I1 term B2 end
    gate I9.I15.I6.I4.I1 term MS end
    gate I9.I15.I6.I4.I2 term F3 end
    gate I9.I15.I6.I4.I1 term F1 end
    gate I9.I2 term A5 end
    gate I5.I7.I2 term PS end
  end
  net count[12]
    gate I9.I15.I6.I4.I2 term NS end
    gate I9.I15.I6.I4.I1 term F3 end
    gate I9.I15.I6.I4.I2 term F5 end
    gate I9.I15.I6.I4.I2 term E1 end
    gate I9.I15.I6.I4.I2 term D2 end
    gate I9.I15.I6.I4.I2 term Q2Z end
    gate I9.I2 term OP end
    gate I5.I7.I2 term E1 end
  end
  net count[11]
    gate I9.I15.I6.I5.I1 term A5 end
    gate I9.I15.I6.I5.I2 term C2 end
    gate I9.I15.I6.I5.I2 term B1 end
    gate I9.I15.I6.I5.I2 term QZ end
    gate I9.I2 term E1 end
    gate I5.I8.I2 term PS end
  end
  net count[10]
    gate I9.I15.I6.I5.I1 term Q2Z end
    gate I9.I15.I6.I5.I1 term E2 end
    gate I9.I15.I6.I5.I1 term D1 end
    gate I9.I15.I6.I5.I2 term F1 end
    gate I9.I2 term NP end
    gate I5.I8.I2 term E1 end
  end
  net count[9]