example_en_24bit_a.chp

VHDL examples for counter design, use QuickLogic eclips

    term PLLCLK_NET port PLLCK end
    term CLKPAD_OUT port PLLOUT end
    term PLL_RESET port PLLRST end
    term PLLCLK_IN port PLLIN end
    term GND end
    term VCC end
  end
  gate PLL_OUTPAD_25UM cell PLLOUTPAD
    term S port SEL end
    term P port IP end
    term A port IZ end
    term GND end
    term VCC end
  end
  gate PLL_RSTPAD_25UM cell PLLRSTPAD
    term Q port IZ end
    term P port IP end
    term GND end
    term VCC end
  end
  gate PLL_CLKPAD_25UM cell CLOCK
    term O port OP end
    term Q port IC end
    term P port IP end
    term GND end
    term VCC end
  end
  gate CLK2HWCLK cell HWCLOCK
    term P port IP end
    term Q port IC end
  end
end
logical example_en_24bit_a
  gates 56
  nets 102
  gate I9.I15.I4.I1 master SUPER_LOGIC end
  gate I9.I15.I4.I2 master SUPER_LOGIC end
  gate I9.I15.I5.I1 master SUPER_LOGIC end
  gate I9.I15.I5.I2 master SUPER_LOGIC end
  gate I9.I16.I6.I4.I1 master SUPER_LOGIC end
  gate I9.I16.I6.I4.I2 master SUPER_LOGIC end
  gate I9.I16.I6.I5.I1 master SUPER_LOGIC end
  gate I9.I16.I6.I5.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I8.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I8.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I9.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I9.I2 master SUPER_LOGIC end
  gate I9.I16.I7.I1 master SUPER_LOGIC end
  gate I9.I16.I7.I2 master SUPER_LOGIC end
  gate I9.I1 master SUPER_LOGIC end
  gate I9.I2 master SUPER_LOGIC end
  gate outpad_25umQ23Q master OUTPAD_25UM end
  gate outpad_25umQ22Q master OUTPAD_25UM end
  gate outpad_25umQ21Q master OUTPAD_25UM end
  gate outpad_25umQ20Q master OUTPAD_25UM end
  gate outpad_25umQ19Q master OUTPAD_25UM end
  gate outpad_25umQ18Q master OUTPAD_25UM end
  gate outpad_25umQ17Q master OUTPAD_25UM end
  gate outpad_25umQ16Q master OUTPAD_25UM end
  gate outpad_25umQ15Q master OUTPAD_25UM end
  gate outpad_25umQ14Q master OUTPAD_25UM end
  gate outpad_25umQ13Q master OUTPAD_25UM end
  gate outpad_25umQ12Q master OUTPAD_25UM end
  gate outpad_25umQ11Q master OUTPAD_25UM end
  gate outpad_25umQ10Q master OUTPAD_25UM end
  gate outpad_25umQ9Q master OUTPAD_25UM end
  gate outpad_25umQ8Q master OUTPAD_25UM end
  gate outpad_25umQ7Q master OUTPAD_25UM end
  gate outpad_25umQ6Q master OUTPAD_25UM end
  gate outpad_25umQ5Q master OUTPAD_25UM end
  gate outpad_25umQ4Q master OUTPAD_25UM end
  gate outpad_25umQ3Q master OUTPAD_25UM end
  gate outpad_25umQ2Q master OUTPAD_25UM end
  gate outpad_25umQ1Q master OUTPAD_25UM end
  gate outpad_25umQ0Q master OUTPAD_25UM end
  gate I1 master INPAD_25UM end
  gate I2 master CKPAD_25UM end
  gate I3 master CLK2HWCLK end
  gate I4.I3.I2 master SUPER_LOGIC end
  gate I4.I4.I2 master SUPER_LOGIC end
  gate I4.I5.I2 master SUPER_LOGIC end
  gate I4.I6.I2 master SUPER_LOGIC end
  gate I5.I6.I2 master SUPER_LOGIC end
  gate I5.I7.I2 master SUPER_LOGIC end
  gate I5.I8.I2 master SUPER_LOGIC end
  gate I5.I9.I2 master SUPER_LOGIC end
  gate I5.I2.I2 master SUPER_LOGIC end
  gate I5.I3.I2 master SUPER_LOGIC end
  gate I5.I4.I2 master SUPER_LOGIC end
  gate I5.I5.I2 master SUPER_LOGIC end
  gate I6.I2 master SUPER_LOGIC end
  net clear_in direction INPUT
    gate I2 term P end
  end
  net clk_in direction INPUT
    gate I3 term P end
  end
  net enable_in direction INPUT
    gate I1 term P end
  end
  net count_val[0] direction OUTPUT
    gate outpad_25umQ0Q term P end
  end
  net count_val[1] direction OUTPUT
    gate outpad_25umQ1Q term P end
  end
  net count_val[2] direction OUTPUT
    gate outpad_25umQ2Q term P end
  end
  net count_val[3] direction OUTPUT
    gate outpad_25umQ3Q term P end
  end
  net count_val[4] direction OUTPUT
    gate outpad_25umQ4Q term P end
  end
  net count_val[5] direction OUTPUT
    gate outpad_25umQ5Q term P end
  end
  net count_val[6] direction OUTPUT
    gate outpad_25umQ6Q term P end
  end
  net count_val[7] direction OUTPUT
    gate outpad_25umQ7Q term P end
  end
  net count_val[8] direction OUTPUT
    gate outpad_25umQ8Q term P end
  end
  net count_val[9] direction OUTPUT
    gate outpad_25umQ9Q term P end
  end
  net count_val[10] direction OUTPUT
    gate outpad_25umQ10Q term P end
  end
  net count_val[11] direction OUTPUT
    gate outpad_25umQ11Q term P end
  end
  net count_val[12] direction OUTPUT
    gate outpad_25umQ12Q term P end
  end
  net count_val[13] direction OUTPUT
    gate outpad_25umQ13Q term P end
  end
  net count_val[14] direction OUTPUT
    gate outpad_25umQ14Q term P end
  end
  net count_val[15] direction OUTPUT
    gate outpad_25umQ15Q term P end
  end
  net count_val[16] direction OUTPUT
    gate outpad_25umQ16Q term P end
  end
  net count_val[17] direction OUTPUT
    gate outpad_25umQ17Q term P end
  end
  net count_val[18] direction OUTPUT
    gate outpad_25umQ18Q term P end
  end
  net count_val[19] direction OUTPUT
    gate outpad_25umQ19Q term P end
  end
  net count_val[20] direction OUTPUT
    gate outpad_25umQ20Q term P end
  end
  net count_val[21] direction OUTPUT
    gate outpad_25umQ21Q term P end
  end
  net count_val[22] direction OUTPUT
    gate outpad_25umQ22Q term P end
  end
  net count_val[23] direction OUTPUT
    gate outpad_25umQ23Q term P end
  end
  net clear clock 3
    gate I9.I16.I7.I9.I2 term QR end
    gate I9.I16.I7.I9.I1 term QR end
    gate I9.I16.I7.I8.I2 term QR end
    gate I9.I16.I7.I8.I1 term QR end
    gate I9.I16.I6.I5.I2 term QR end
    gate I9.I16.I6.I5.I1 term QR end
    gate I9.I16.I6.I4.I2 term QR end
    gate I9.I16.I6.I4.I1 term QR end
    gate I9.I15.I5.I2 term QR end
    gate I9.I15.I5.I1 term QR end
    gate I9.I15.I4.I2 term QR end
    gate I9.I15.I4.I1 term QR end
    gate I2 term Q end
  end
  net clk clock 1
    gate I4.I3.I2 term DCLK end
    gate I4.I4.I2 term DCLK end
    gate I4.I5.I2 term DCLK end
    gate I4.I6.I2 term DCLK end
    gate I5.I2.I2 term DCLK end
    gate I5.I3.I2 term DCLK end
    gate I5.I4.I2 term DCLK end
    gate I5.I5.I2 term DCLK end
    gate I5.I6.I2 term DCLK end
    gate I5.I7.I2 term DCLK end
    gate I5.I8.I2 term DCLK end
    gate I5.I9.I2 term DCLK end
    gate I6.I2 term DCLK end
    gate I9.I15.I4.I1 term DCLK end
    gate I9.I15.I4.I2 term DCLK end
    gate I9.I15.I5.I1 term DCLK end
    gate I9.I15.I5.I2 term DCLK end
    gate I9.I16.I6.I4.I1 term DCLK end
    gate I9.I16.I6.I4.I2 term DCLK end
    gate I9.I16.I6.I5.I1 term DCLK end
    gate I9.I16.I6.I5.I2 term DCLK end
    gate I9.I16.I7.I8.I1 term DCLK end
    gate I9.I16.I7.I8.I2 term DCLK end
    gate I9.I16.I7.I9.I1 term DCLK end
    gate I9.I16.I7.I9.I2 term DCLK end
    gate I3 term Q end
  end
  net enable_reg
    gate I9.I16.I7.I8.I2 term D1 end
    gate I9.I16.I7.I8.I2 term E2 end
    gate I9.I16.I7.I8.I2 term MP end
    gate I9.I16.I7.I8.I1 term F1 end
    gate I9.I16.I7.I1 term F5 end
    gate I9.I1 term F5 end
    gate I6.I2 term QZ end
  end
  net count[0]
    gate I9.I16.I7.I8.I2 term D2 end
    gate I9.I16.I7.I8.I2 term E1 end
    gate I9.I16.I7.I8.I2 term F5 end
    gate I9.I16.I7.I8.I2 term NS end
    gate I9.I16.I7.I8.I1 term F3 end
    gate I9.I16.I7.I1 term A1 end
    gate I9.I1 term F1 end
    gate I4.I5.I2 term E1 end
    gate I9.I16.I7.I8.I2 term Q2Z end
  end
  net count[1]
    gate I9.I16.I7.I8.I2 term F3 end
    gate I9.I16.I7.I8.I1 term B2 end
    gate I9.I16.I7.I8.I1 term C1 end
    gate I9.I16.I7.I8.I1 term MS end
    gate I9.I16.I7.I8.I1 term NP end
    gate I9.I16.I7.I1 term A3 end
    gate I9.I1 term NP end
    gate I4.I5.I2 term PS end
    gate I9.I16.I7.I8.I1 term QZ end
  end
  net count[2]
    gate I9.I16.I7.I8.I2 term F1 end
    gate I9.I16.I7.I8.I1 term D1 end
    gate I9.I16.I7.I8.I1 term E2 end
    gate I9.I16.I7.I1 term A5 end
    gate I9.I1 term E1 end
    gate I4.I6.I2 term E1 end
    gate I9.I16.I7.I8.I1 term Q2Z end
  end
  net count[3]
    gate I9.I16.I7.I8.I2 term B1 end
    gate I9.I16.I7.I8.I2 term C2 end
    gate I9.I16.I7.I8.I1 term A5 end
    gate I9.I16.I7.I2 term A1 end
    gate I9.I1 term OP end
    gate I4.I6.I2 term PS end
    gate I9.I16.I7.I8.I2 term QZ end
  end
  net count[4]
    gate I9.I16.I7.I9.I2 term D2 end
    gate I9.I16.I7.I9.I2 term E1 end
    gate I9.I16.I7.I9.I2 term F5 end
    gate I9.I16.I7.I9.I2 term NS end
    gate I9.I16.I7.I9.I1 term F3 end
    gate I9.I16.I7.I2 term A3 end
    gate I9.I1 term A5 end
    gate I4.I4.I2 term E1 end
    gate I9.I16.I7.I9.I2 term Q2Z end
  end
  net count[5]
    gate I9.I16.I7.I9.I2 term F3 end
    gate I9.I16.I7.I9.I1 term B2 end
    gate I9.I16.I7.I9.I1 term C1 end
    gate I9.I16.I7.I9.I1 term MS end
    gate I9.I16.I7.I9.I1 term NP end
    gate I9.I16.I7.I2 term A5 end
    gate I9.I1 term A3 end
    gate I4.I4.I2 term PS end
    gate I9.I16.I7.I9.I1 term QZ end
  end
  net count[6]
    gate I9.I16.I7.I9.I2 term F1 end
    gate I9.I16.I7.I9.I1 term D1 end
    gate I9.I16.I7.I9.I1 term E2 end
    gate I9.I16.I7.I1 term F1 end
    gate I9.I1 term A1 end
    gate I4.I3.I2 term E1 end
    gate I9.I16.I7.I9.I1 term Q2Z end
  end
  net count[7]
    gate I9.I16.I7.I9.I2 term B1 end
    gate I9.I16.I7.I9.I2 term C2 end
    gate I9.I16.I7.I9.I1 term A5 end
    gate I9.I16.I7.I1 term F3 end
    gate I9.I2 term F5 end
    gate I4.I3.I2 term PS end
    gate I9.I16.I7.I9.I2 term QZ end
  end
  net count[8]
    gate I9.I16.I6.I5.I2 term D2 end
    gate I9.I16.I6.I5.I2 term E1 end
    gate I9.I16.I6.I5.I2 term F5 end
    gate I9.I16.I6.I5.I2 term NS end
    gate I9.I16.I6.I5.I1 term F3 end
    gate I9.I2 term F3 end
    gate I5.I5.I2 term E1 end
    gate I9.I16.I6.I5.I2 term Q2Z end
  end
  net count[9]
    gate I9.I16.I6.I5.I2 term F3 end
    gate I9.I16.I6.I5.I1 term B2 end
    gate I9.I16.I6.I5.I1 term C1 end
    gate I9.I16.I6.I5.I1 term MS end
    gate I9.I16.I6.I5.I1 term NP end
    gate I9.I2 term F1 end
    gate I5.I5.I2 term PS end
    gate I9.I16.I6.I5.I1 term QZ end
  end
  net count[10]
    gate I9.I16.I6.I5.I2 term F1 end
    gate I9.I16.I6.I5.I1 term D1 end
    gate I9.I16.I6.I5.I1 term E2 end
    gate I9.I2 term NP end
    gate I5.I4.I2 term E1 end
    gate I9.I16.I6.I5.I1 term Q2Z end
  end
  net count[11]
    gate I9.I16.I6.I5.I2 term B1 end
    gate I9.I16.I6.I5.I2 term C2 end
    gate I9.I16.I6.I5.I1 term A5 end
    gate I9.I2 term E1 end
    gate I5.I4.I2 term PS end
    gate I9.I16.I6.I5.I2 term QZ end
  end
  net count[12]
    gate I9.I16.I6.I4.I2 term D2 end
    gate I9.I16.I6.I4.I2 term E1 end
    gate I9.I16.I6.I4.I2 term F5 end
    gate I9.I16.I6.I4.I2 term NS end
    gate I9.I16.I6.I4.I1 term F3 end
    gate I9.I2 term OP end
    gate I5.I3.I2 term E1 end
    gate I9.I16.I6.I4.I2 term Q2Z end
  end
  net count[13]
    gate I9.I16.I6.I4.I2 term F3 end
    gate I9.I16.I6.I4.I1 term B2 end
    gate I9.I16.I6.I4.I1 term C1 end
    gate I9.I16.I6.I4.I1 term MS end
    gate I9.I16.I6.I4.I1 term NP end
    gate I9.I2 term A5 end
    gate I5.I3.I2 term PS end
    gate I9.I16.I6.I4.I1 term QZ end
  end
  net count[14]
    gate I9.I16.I6.I4.I2 term F1 end
    gate I9.I16.I6.I4.I1 term D1 end
    gate I9.I16.I6.I4.I1 term E2 end
    gate I9.I2 term A3 end
    gate I5.I2.I2 term E1 end
    gate I9.I16.I6.I4.I1 term Q2Z end
  end
  net count[15]
    gate I9.I16.I6.I4.I2 term B1 end
    gate I9.I16.I6.I4.I2 term C2 end
    gate I9.I16.I6.I4.I1 term A5 end
    gate I9.I2 term A1 end
    gate I5.I2.I2 term PS end
    gate I9.I16.I6.I4.I2 term QZ end
  end
  net count[16]
    gate I9.I15.I5.I2 term D2 end
    gate I9.I15.I5.I2 term E1 end
    gate I9.I15.I5.I2 term F5 end
    gate I9.I15.I5.I2 term NS end
    gate I9.I15.I5.I1 term F3 end
    gate I5.I9.I2 term E1 end
    gate I9.I15.I5.I2 term Q2Z end
  end
  net count[17]
    gate I9.I15.I5.I2 term F3 end
    gate I9.I15.I5.I1 term B2 end
    gate I9.I15.I5.I1 term C1 end
    gate I9.I15.I5.I1 term MS end
    gate I9.I15.I5.I1 term NP end
    gate I5.I9.I2 term PS end
    gate I9.I15.I5.I1 term QZ end
  end
  net count[18]
    gate I9.I15.I5.I2 term F1 end
    gate I9.I15.I5.I1 term D1 end
    gate I9.I15.I5.I1 term E2 end
    gate I5.I8.I2 term E1 end
    gate I9.I15.I5.I1 term Q2Z end
  end
  net count[19]
    gate I9.I15.I5.I2 term B1 end
    gate I9.I15.I5.I2 term C2 end
    gate I9.I15.I5.I1 term A5 end
    gate I5.I8.I2 term PS end
    gate I9.I15.I5.I2 term QZ end
  end
  net count[20]
    gate I9.I15.I4.I2 term D2 end
    gate I9.I15.I4.I2 term E1 end
    gate I9.I15.I4.I2 term F5 end
    gate I9.I15.I4.I2 term NS end
    gate I9.I15.I4.I1 term F3 end
    gate I5.I7.I2 term E1 end
    gate I9.I15.I4.I2 term Q2Z end
  end
  net count[21]
    gate I9.I15.I4.I2 term F3 end
    gate I9.I15.I4.I1 term B2 end
    gate I9.I15.I4.I1 term C1 end
    gate I9.I15.I4.I1 term MS end
    gate I9.I15.I4.I1 term NP end
    gate I5.I7.I2 term PS end
    gate I9.I15.I4.I1 term QZ end
  end
  net count[22]
    gate I9.I15.I4.I2 term F1 end
    gate I9.I15.I4.I1 term D1 end
    gate I9.I15.I4.I1 term E2 end
    gate I5.I6.I2 term E1 end
    gate I9.I15.I4.I1 term Q2Z end
  end
  net count[23]
    gate I9.I15.I4.I2 term B1 end
    gate I9.I15.I4.I2 term C2 end
    gate I9.I15.I4.I1 term A5 end
    gate I5.I6.I2 term PS end
    gate I9.I15.I4.I2 term QZ end
  end
  net count_out[23]
    gate outpad_25umQ23Q term A end
    gate I5.I6.I2 term Q2Z end
  end
  net count_out[22]
    gate outpad_25umQ22Q term A end
    gate I5.I6.I2 term QZ end
  end
  net count_out[21]
    gate outpad_25umQ21Q term A end
    gate I5.I7.I2 term Q2Z end
  end
  net count_out[20]
    gate outpad_25umQ20Q term A end
    gate I5.I7.I2 term QZ end
  end
  net count_out[19]
    gate outpad_25umQ19Q term A end
    gate I5.I8.I2 term Q2Z end
  end
  net count_out[18]
    gate outpad_25umQ18Q term A end
    gate I5.I8.I2 term QZ end
  end
  net count_out[17]
    gate outpad_25umQ17Q term A end
    gate I5.I9.I2 term Q2Z end
  end
  net count_out[16]
    gate outpad_25umQ16Q term A end
    gate I5.I9.I2 term QZ end
  end
  net count_out[15]
    gate outpad_25umQ15Q term A end
    gate I5.I2.I2 term Q2Z end
  end
  net count_out[14]
    gate outpad_25umQ14Q term A end
    gate I5.I2.I2 term QZ end
  end
  net count_out[13]
    gate outpad_25umQ13Q term A end