example_en_24bit_a.rpt

VHDL examples for counter design, use QuickLogic eclips

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| Design Information |
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Design:            example_en_24bit_a
SpDE Version:      SpDE 9.5 Release Build2
Report Generated:  Thu Aug 14 11:05:38 2003
CHIP Last Updated: Thu Aug 14 11:00:21 2003
Part Type:         ql8325
Speed Grade:       8
Operating Range:   Commercial
Package Type:      484 PIN PBGA
Link Check Sum: Undetermined: sequencer has not yet been run

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| Utilization Information |
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Utilized cells (preplacement):                  28 of    1536  (1.8%)
Utilized cells (postplacement):                 28 of    1536  (1.8%)
Utilized Logic cell Frags (preplacement):      128 of    9216  (1.4%)
Utilized Logic cell Frags (postplacement):     139 of    9216  (1.5%)
Utilized Fragment A :                           19
Utilized Fragment F :                           19
Utilized Fragment O :                           26
Utilized Fragment N :                           26
IO control cells:                                0 of      16  (0.0%)
Clock only cells:                                2 of       9  (22.2%)
Bi directional cells:                           25 of     310  (8.1%)
RAM cells:                                       0 of      24  (0.0%)
ECU cells:                                       0 of      12  (0.0%)
PLL cells:                                       0 of       4  (0.0%)
Flip-Flop of IO cells:                           0 of     316  (0.0%)
1st Flip-Flop of Logic cells:                   24 of    1536  (1.6%)
2nd Flip-Flop of Logic cells:                   25 of    1536  (1.6%)
Routing resources:                             603 of  119527  (0.5%)
ViaLink resources:                             489 of 3213992  (0.0%)



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| Clock Network Utilization by clock pads |
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	Clock Network                  Net                                  Pin      Quad                  Load    
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	PLLMUX_TL4                     clear                                L3       Top Left               7       
	PLLMUX_TL2                     clk                                  L1       Top Left               25      


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| Clock Network Utilization by Internal Logic |
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| Clock Network Utilization by PLL |
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|Available HSCK Clock Networks|
	Quad TOP LEFT     : 	5 of 5 QuadNets available	(100.0%)
	Quad TOP RIGHT    : 	5 of 5 QuadNets available	(100.0%)
	Quad BOTTOM LEFT  : 	5 of 5 QuadNets available	(100.0%)
	Quad BOTTOM RIGHT : 	5 of 5 QuadNets available	(100.0%)




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| Timing Results |
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Summary:

Clock                               Frequency       Setup Time      Clock to Out   
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clk_in                          252 MHz /  4.0 ns      2.7 ns          4.0 ns


Inter Clock Domain Delay Matrix
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Clock0 = clk_in 

 
          Clock0  
Clock0    4.0 ns

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| Tools run on design example_en_24bit_a |
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partdef         9.4    
design          9.5    
logic optimizer 9.5     Mode = Quality Goal = Speed IgnorePack = FALSE UseNonBondedPads = TRUE Run Time 0:00:01
placer          9.5     Seed = 42 Mode = Quality Run Time 0:00:11
router          9.51    Seed = 42 Run Time 0:00:01
delay modeler   9.5     Mode = Commercial Corner = Worst SpeedGrade = 8 LowPower = FALSE Run Time 0:00:01
back annotation 9.5     Run Time 0:00:02
verifier        9.5    
auto buffer     9.5    


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| Pin Table |
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Display Pin Info option is FALSE.
Pin information will not be displayed.

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| Fixed Flip Flops |
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None


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| Fixed RAM cells |
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None


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| Fixed ECU cells |
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None


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| Nets Removed by Technology Mapper |
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Removed Nets option is FALSE.
Removed Nets information will not be displayed.



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