example_en_16bit_a.v

VHDL examples for counter design, use QuickLogic eclips

eio_cell I1 ( .EQE(VCC), .ESEL(VCC), .IE(VCC), .IP(P), .IQC(GND), .IQE(GND),
           .IQR(GND), .OQI(A), .OSEL(VCC) );

endmodule // outpad_25um

`endif

`ifdef eio_cell
`else
`define eio_cell
module eio_cell( EQE , ESEL, IE, IQC, IQE, IQR, OQI, OSEL, IQQ, IZ, OQQ, IP );
input EQE, ESEL, IE;
inout IP;
input IQC, IQE;
output IQQ;
input IQR;
output IZ;
input OQI;
output OQQ;
input OSEL;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute eio_cell noopt true 
 wire EQMUX_Z, OQMUX_Z;  
 reg EQZ, OQQ, IQQ;  
 assign #1 EQMUX_Z = ESEL ? IE : EQZ;  
 assign #1 OQMUX_Z = OSEL ? OQI : OQQ;  
 assign #1 IP = EQMUX_Z ? OQMUX_Z : 1'bz;  
 assign #1 IZ = IP;  
 
`ifdef synthesis  
  always @ (posedge IQC or posedge IQR)  
    if (IQR) 
      #1 EQZ = 1'b0; 
    else if (EQE) 
      #1 EQZ = IE;  
  always @ (posedge IQC or posedge IQR)  
    if (IQR) 
      #1 IQQ = 1'b0;  
    else if (IQE)  
      #1 IQQ = IP;  
  always @ (posedge IQC or posedge IQR)  
    if (IQR)  
      #1 OQQ = 1'b0;  
    else  
      #1 OQQ = OQI;  
`else  
/* synopsys translate_off */
  always @ (posedge IQC)  
    if (~IQR & EQE) 
      #1 EQZ = IE;  
    else if (IQR)  
      #1 EQZ = 1'b0; 
  always @ (posedge IQC)  
    if (~IQR & IQE)  
      #1 IQQ = IP;  
    else if (IQR)  
      #1 IQQ = 1'b0;  always @ (posedge IQC)  
    if (~IQR)  
      #1 OQQ = OQI;  
    else if (IQR)  
      #1 OQQ = 1'b0;  
/* synopsys translate_on */
`endif  
 

endmodule // eio_cell

`endif

`ifdef ckcell_25um
`else
`define ckcell_25um
module ckcell_25um( IP , IC );
output IC;
input IP;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute ckcell_25um noopt true 
 assign #1 IC = IP;

endmodule // ckcell_25um

`endif

`ifdef super_logic
`else
`define super_logic
module super_logic( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                    F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC,
                    QR, QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC /* synthesis syn_isclock=1 */;
//exemplar attribute QC syn_isclock true
input QR, QS;
output QZ;
// exemplar attribute super_logic dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `LOGIC;

super_cell I2 ( .A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .AZ(AZ),
             .B1(B1), .B2(B2), .C1(C1), .C2(C2), .D1(D1), .D2(D2), .E1(E1),
             .E2(E2), .F1(F1), .F2(F2), .F3(F3), .F4(F4), .F5(F5), .F6(F6),
             .FZ(FZ), .MP(MP), .MS(MS), .NP(NP), .NS(NS), .NZ(NZ), .OP(OP),
             .OS(OS), .OZ(OZ), .PP(PP), .PS(PS), .Q2Z(Q2Z), .QC(QC), .QR(QR),
             .QS(QS), .QZ(QZ) );

endmodule // super_logic

`endif

`ifdef counter_en_h4bit
`else
`define counter_en_h4bit
module counter_en_h4bit( clear , clk, enable, enablehbit_a, qa_r, qb_r, qc_r, qd_r );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
input enable;
output enablehbit_a, qa_r, qb_r, qc_r, qd_r;
// exemplar attribute counter_en_h4bit dont_touch true 
parameter syn_macro = 1;
wire ED_a;
wire BCD_a;
supply0 GND;
supply1 VCC;

super_logic I1 ( .A1(BCD_a), .A2(GND), .A3(ED_a), .A4(GND), .A5(qa_r), .A6(GND),
              .AZ(enablehbit_a), .B1(ED_a), .B2(qc_r), .C1(qc_r), .C2(ED_a),
              .D1(qb_r), .D2(GND), .E1(VCC), .E2(qb_r), .F1(enable), .F2(GND),
              .F3(qd_r), .F4(GND), .F5(VCC), .F6(GND), .FZ(ED_a), .MP(GND),
              .MS(qc_r), .NP(qc_r), .NS(GND), .OP(GND), .OS(GND), .PP(GND),
              .PS(GND), .Q2Z(qb_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qc_r), .NZ(), .OZ() );
super_logic I2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND),
              .B1(qa_r), .B2(GND), .C1(VCC), .C2(qa_r), .D1(enable), .D2(qd_r),
              .E1(qd_r), .E2(enable), .F1(qb_r), .F2(GND), .F3(qc_r), .F4(GND),
              .F5(qd_r), .F6(GND), .FZ(BCD_a), .MP(enable), .MS(GND), .NP(GND),
              .NS(qd_r), .OP(GND), .OS(GND), .PP(GND), .PS(GND), .Q2Z(qd_r),
              .QC(clk), .QR(clear), .QS(GND), .QZ(qa_r), .AZ(), .NZ(), .OZ() );

endmodule // counter_en_h4bit

`endif

`ifdef counter_en_4bit
`else
`define counter_en_4bit
module counter_en_4bit( clear , clk, enable, qa_r, qb_r, qc_r, qd_r );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
input enable;
output qa_r, qb_r, qc_r, qd_r;
// exemplar attribute counter_en_4bit dont_touch true 
parameter syn_macro = 1;
wire ED_a;
wire ABCDE_a;
wire BCD_a;
supply0 GND;
supply1 VCC;

super_logic I1 ( .A1(BCD_a), .A2(GND), .A3(ED_a), .A4(GND), .A5(qa_r), .A6(GND),
              .AZ(ABCDE_a), .B1(ED_a), .B2(qc_r), .C1(qc_r), .C2(ED_a),
              .D1(qb_r), .D2(GND), .E1(VCC), .E2(qb_r), .F1(enable), .F2(GND),
              .F3(qd_r), .F4(GND), .F5(VCC), .F6(GND), .FZ(ED_a), .MP(GND),
              .MS(qc_r), .NP(qc_r), .NS(GND), .OP(GND), .OS(GND), .PP(GND),
              .PS(GND), .Q2Z(qb_r), .QC(clk), .QR(clear), .QS(GND), .QZ(qc_r), .NZ(), .OZ() );
super_logic I2 ( .A1(VCC), .A2(GND), .A3(VCC), .A4(GND), .A5(VCC), .A6(GND),
              .B1(qa_r), .B2(GND), .C1(VCC), .C2(qa_r), .D1(enable), .D2(qd_r),
              .E1(qd_r), .E2(enable), .F1(qb_r), .F2(GND), .F3(qc_r), .F4(GND),
              .F5(qd_r), .F6(GND), .FZ(BCD_a), .MP(enable), .MS(GND), .NP(GND),
              .NS(qd_r), .OP(GND), .OS(GND), .PP(GND), .PS(GND), .Q2Z(qd_r),
              .QC(clk), .QR(clear), .QS(GND), .QZ(qa_r), .AZ(), .NZ(), .OZ() );

endmodule // counter_en_4bit

`endif

`ifdef super_cell
`else
`define super_cell
module super_cell( A1 , A2, A3, A4, A5, A6, B1, B2, C1, C2, D1, D2, E1, E2, F1,
                   F2, F3, F4, F5, F6, MP, MS, NP, NS, OP, OS, PP, PS, QC, QR,
                   QS, AZ, FZ, NZ, OZ, Q2Z, QZ );
input A1, A2, A3, A4, A5, A6;
output AZ;
input B1, B2, C1, C2, D1, D2, E1, E2, F1, F2, F3, F4, F5, F6;
output FZ;
input MP, MS, NP, NS;
output NZ;
input OP, OS;
output OZ;
input PP, PS;
output Q2Z;
input QC, QR, QS;
output QZ;
parameter syn_macro = 1;
parameter ql_frag = 1;
// exemplar attribute super_cell noopt true 
 wire TOPMUX_Z, MIDMUX_Z, BOTMUX_Z, FFMUX_Z, CLKMUX_Z; 
 wire MZ; 
 reg QZ, Q2Z; 
 
 assign #1 AZ = A1 & ~A2 & A3 & ~A4 & A5 & ~A6; 
 assign #1 TOPMUX_Z = OP ? AZ : OS; 
 assign #1 MZ = MIDMUX_Z ? (C1 & ~C2) : (B1 & ~B2); 
 assign #1 MIDMUX_Z = MP ? FZ : MS; 
 assign #1 NZ = BOTMUX_Z ? (E1 & ~E2) : (D1 & ~D2); 
 assign #1 BOTMUX_Z = NP ? FZ : NS; 
 assign #1 FZ = F1 & ~F2 & F3 & ~F4 & F5 & ~F6; 
 assign #1 OZ = TOPMUX_Z ? NZ : MZ; 
 assign #1 FFMUX_Z = PP ? PS : NZ; 
`ifdef synthesis 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
     else 
        #1 QZ = OZ; 
  always @ (posedge QC or posedge QR or posedge QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
     else 
        #1 Q2Z = FFMUX_Z; 
`else 
/* synopsys translate_off */
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 QZ = OZ; 
  always @ (QR or QS) 
     if (QR) 
        #1 QZ = 1'b0; 
     else if (QS) 
        #1 QZ = 1'b1; 
  always @ (posedge QC) 
     if (~QR && ~QS) 
        #1 Q2Z = FFMUX_Z; 
  always @ (QR or QS) 
     if (QR) 
        #1 Q2Z = 1'b0; 
     else if (QS) 
        #1 Q2Z = 1'b1; 
/* synopsys translate_on */
`endif 

endmodule // super_cell

`endif