example_en_16bit_a.v

VHDL examples for counter design, use QuickLogic eclips

/* Verilog Model Created from SCS Schematic example_en_16bit_a.sch 
   Aug 18, 2004 17:02 */

/* Automatically generated by hvveri version 9.6.2 Release Build2 */
`ifdef exemplar
	`ifdef synthesis
	`else
	`define synthesis
	`endif
`endif

`timescale 1ns/1ns  
`define LOGIC   1 
`define BIDIR   2 
`define INCELL  3 
`define CLOCK   4 
`define HSCK    5 
`define CLOCKB  6 
`define ESPXCLKIN  7 
`define HSCKMUX 8 
`define IOCONTROL 9 

module example_en_16bit_a( clear_in , clk_in, enable_in, count_out );
input clear_in;
input clk_in /* synthesis syn_isclock=1 */;
//exemplar attribute clk_in syn_isclock true
 output [15:0] count_out;
input enable_in;
// exemplar attribute example_en_16bit_a dont_touch true 
parameter syn_macro = 1;
wire [15:0] count_reg;
wire [15:0] count;
wire enable_reg;
wire enable;
wire clear;
wire clk;

counter_en_16bit_a I9 ( .clear(clear), .clk(clk), .count({ count[15:0] }),
                     .enable(enable_reg) );
opad16_25um I1 ( .A({ count_reg[15:0] }), .P({ count_out[15:0] }) );
inpad_25um I2 ( .P(enable_in), .Q(enable) );
ckpad_25um I3 ( .P(clear_in), .Q(clear) );
ckpad_25um I4 ( .P(clk_in), .Q(clk) );
rg16_25um I5 ( .CLK(clk), .D({ count[15:0] }), .Q({ count_reg[15:0] }) );
dff_2 I6 ( .CLK(clk), .D1(enable), .D2(enable), .Q1(enable_reg) );

endmodule // example_en_16bit_a


`ifdef counter_en_16bit_a
`else
`define counter_en_16bit_a
module counter_en_16bit_a( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [15:0] count;
input enable;
// exemplar attribute counter_en_16bit_a dont_touch true 
parameter syn_macro = 1;
wire enable_8bit_h;

counter_en_8bit_a_ii I6 ( .clear(clear), .clk(clk), .count({ count[15:8] }),
                       .enable(enable_8bit_h) );
counter_en_8bit_a_i I7 ( .clear(clear), .clk(clk), .count({ count[7:0] }),
                      .en_8bit_a(enable_8bit_h), .enable(enable) );

endmodule // counter_en_16bit_a

`endif

`ifdef opad16_25um
`else
`define opad16_25um
module opad16_25um( A , P );
 input [15:0] A;
 output [15:0] P;
// exemplar attribute opad16_25um dont_touch true 
parameter syn_macro = 1;

outpad_25um I1 ( .A(A[0]), .P(P[0]) );
outpad_25um I2 ( .A(A[1]), .P(P[1]) );
outpad_25um I3 ( .A(A[2]), .P(P[2]) );
outpad_25um I4 ( .A(A[3]), .P(P[3]) );
outpad_25um I5 ( .A(A[4]), .P(P[4]) );
outpad_25um I6 ( .A(A[5]), .P(P[5]) );
outpad_25um I7 ( .A(A[6]), .P(P[6]) );
outpad_25um I8 ( .A(A[7]), .P(P[7]) );
outpad_25um I9 ( .A(A[8]), .P(P[8]) );
outpad_25um I10 ( .A(A[9]), .P(P[9]) );
outpad_25um I11 ( .A(A[10]), .P(P[10]) );
outpad_25um I12 ( .A(A[11]), .P(P[11]) );
outpad_25um I13 ( .A(A[12]), .P(P[12]) );
outpad_25um I14 ( .A(A[13]), .P(P[13]) );
outpad_25um I15 ( .A(A[14]), .P(P[14]) );
outpad_25um I16 ( .A(A[15]), .P(P[15]) );

endmodule // opad16_25um

`endif

`ifdef inpad_25um
`else
`define inpad_25um
module inpad_25um( P , Q );
input P;
output Q;
// exemplar attribute inpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 gnd;
supply1 vcc;

eio_cell I1 ( .EQE(vcc), .ESEL(vcc), .IE(gnd), .IP(P), .IQC(gnd), .IQE(gnd),
           .IQR(gnd), .IZ(Q), .OQI(vcc), .OSEL(vcc) );

endmodule // inpad_25um

`endif

`ifdef ckpad_25um
`else
`define ckpad_25um
module ckpad_25um( P , Q );
input P /* synthesis syn_isclock=1 */;
//exemplar attribute P syn_isclock true
output Q;
// exemplar attribute ckpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `CLOCK;

ckcell_25um I1 ( .IC(Q), .IP(P) );

endmodule // ckpad_25um

`endif

`ifdef rg16_25um
`else
`define rg16_25um
module rg16_25um( CLK , D, Q );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
 input [15:0] D;
 output [15:0] Q;
// exemplar attribute rg16_25um dont_touch true 
parameter syn_macro = 1;

dff_2 I6 ( .CLK(CLK), .D1(D[14]), .D2(D[15]), .Q1(Q[14]), .Q2(Q[15]) );
dff_2 I7 ( .CLK(CLK), .D1(D[12]), .D2(D[13]), .Q1(Q[12]), .Q2(Q[13]) );
dff_2 I8 ( .CLK(CLK), .D1(D[10]), .D2(D[11]), .Q1(Q[10]), .Q2(Q[11]) );
dff_2 I9 ( .CLK(CLK), .D1(D[8]), .D2(D[9]), .Q1(Q[8]), .Q2(Q[9]) );
dff_2 I2 ( .CLK(CLK), .D1(D[6]), .D2(D[7]), .Q1(Q[6]), .Q2(Q[7]) );
dff_2 I3 ( .CLK(CLK), .D1(D[4]), .D2(D[5]), .Q1(Q[4]), .Q2(Q[5]) );
dff_2 I4 ( .CLK(CLK), .D1(D[2]), .D2(D[3]), .Q1(Q[2]), .Q2(Q[3]) );
dff_2 I5 ( .CLK(CLK), .D1(D[0]), .D2(D[1]), .Q1(Q[0]), .Q2(Q[1]) );

endmodule // rg16_25um

`endif

`ifdef dff_2
`else
`define dff_2
module dff_2( CLK , D1, D2, Q1, Q2 );
input CLK /* synthesis syn_isclock=1 */;
//exemplar attribute CLK syn_isclock true
input D1, D2;
output Q1, Q2;
// exemplar attribute dff_2 dont_touch true 
parameter syn_macro = 1;
supply1 vcc;
supply0 gnd;

super_logic I2 ( .A1(vcc), .A2(gnd), .A3(vcc), .A4(gnd), .A5(vcc), .A6(gnd),
              .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd), .D1(vcc), .D2(gnd),
              .E1(D1), .E2(gnd), .F1(vcc), .F2(gnd), .F3(vcc), .F4(gnd),
              .F5(vcc), .F6(gnd), .MP(gnd), .MS(vcc), .NP(gnd), .NS(vcc),
              .OP(gnd), .OS(vcc), .PP(vcc), .PS(D2), .Q2Z(Q2), .QC(CLK),
              .QR(gnd), .QS(gnd), .QZ(Q1), .AZ(), .FZ(), .NZ(), .OZ() );

endmodule // dff_2

`endif

`ifdef counter_en_8bit_a_ii
`else
`define counter_en_8bit_a_ii
module counter_en_8bit_a_ii( clear , clk, enable, count );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [7:0] count;
input enable;
// exemplar attribute counter_en_8bit_a_ii dont_touch true 
parameter syn_macro = 1;
wire enable_8bit;

counter_en_h4bit I4 ( .clear(clear), .clk(clk), .enable(enable),
                   .enablehbit_a(enable_8bit), .qa_r(count[3]),
                   .qb_r(count[2]), .qc_r(count[1]), .qd_r(count[0]) );
counter_en_4bit I1 ( .clear(clear), .clk(clk), .enable(enable_8bit),
                  .qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
                  .qd_r(count[4]) );

endmodule // counter_en_8bit_a_ii

`endif

`ifdef counter_en_8bit_a_i
`else
`define counter_en_8bit_a_i
module counter_en_8bit_a_i( clear , clk, enable, count, en_8bit_a );
input clear;
input clk /* synthesis syn_isclock=1 */;
//exemplar attribute clk syn_isclock true
 output [7:0] count;
output en_8bit_a;
input enable;
// exemplar attribute counter_en_8bit_a_i dont_touch true 
parameter syn_macro = 1;
wire en_8bit3_a;
wire en_8bit2_a;
wire en_8bit1_a;
wire enableh4bit;
supply1 vcc;
supply0 gnd;

counter_en_h4bit I8 ( .clear(clear), .clk(clk), .enable(enable),
                   .enablehbit_a(enableh4bit), .qa_r(count[3]),
                   .qb_r(count[2]), .qc_r(count[1]), .qd_r(count[0]) );
counter_en_h4bit I7 ( .clear(clear), .clk(clk), .enable(enableh4bit),
                   .qa_r(count[7]), .qb_r(count[6]), .qc_r(count[5]),
                   .qd_r(count[4]) );
super_logic I1 ( .A1(count[0]), .A2(gnd), .A3(count[1]), .A4(gnd), .A5(count[2]),
              .A6(gnd), .AZ(en_8bit1_a), .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd),
              .D1(vcc), .D2(gnd), .E1(vcc), .E2(gnd), .F1(count[6]), .F2(gnd),
              .F3(count[7]), .F4(gnd), .F5(enable), .F6(gnd), .FZ(en_8bit2_a),
              .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd), .OP(gnd), .OS(gnd),
              .PP(gnd), .PS(gnd), .QC(gnd), .QR(gnd), .QS(gnd), .NZ(), .OZ(), .Q2Z(), .QZ() );
super_logic I2 ( .A1(count[3]), .A2(gnd), .A3(count[4]), .A4(gnd), .A5(count[5]),
              .A6(gnd), .AZ(en_8bit3_a), .B1(vcc), .B2(gnd), .C1(vcc), .C2(gnd),
              .D1(vcc), .D2(gnd), .E1(vcc), .E2(gnd), .F1(en_8bit1_a), .F2(gnd),
              .F3(en_8bit2_a), .F4(gnd), .F5(en_8bit3_a), .F6(gnd),
              .FZ(en_8bit_a), .MP(gnd), .MS(gnd), .NP(gnd), .NS(gnd), .OP(gnd),
              .OS(gnd), .PP(gnd), .PS(gnd), .QC(gnd), .QR(gnd), .QS(gnd), .NZ(), .OZ(), .Q2Z(), .QZ() );

endmodule // counter_en_8bit_a_i

`endif

`ifdef outpad_25um
`else
`define outpad_25um
module outpad_25um( A , P );
input A;
output P;
// exemplar attribute outpad_25um dont_touch true 
parameter syn_macro = 1;
parameter ql_gate = `BIDIR;
supply0 GND;
supply1 VCC;