example_en_16bit_a.vh

来自「VHDL examples for counter design, use Qu」· VH 代码 · 共 11 行

module example_en_16bit_a (
  clear_in,
  clk_in,
  enable_in,
  count_out
);
input clear_in ;
input clk_in ;
input enable_in ;
output [15:0] count_out /* synthesis syn_tristate = 1 */;