example_en_16bit_a.sc

来自「VHDL examples for counter design, use Qu」· SC 代码 · 共 16 行

#example_en_16bit_a.sc
#Synplicity Synthesis command file
#Automatically generated by ecs2spde version 9.6.2 Release Build2
#Date: 8/18/2004 at 16:57

#To turn off all Synplicity buffer insertion, uncommment the following line:
#option quicklogic ql_nobuffer=1;

#To turn off Synplicity buffer insertion on a pad
#by pad basis, use the following format per pad net:
#portprop net_name             ql_nobuffer=1;


#Include fixed I/O & FF placements from SCS or SpDE
include "example_en_16bit_a.scp";