example_en_16bit_a.srr

VHDL examples for counter design, use QuickLogic eclips

$ Start of Compile
#Wed Aug 18 17:03:10 2004

Synplicity VHDL Compiler, version Compilers 2.6.0, Build 102R, built Jan 27 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@N:"C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.vhd":438:7:438:24|Top entity is set to example_en_16bit_a.
VHDL syntax check successful!
Synthesizing work.example_en_16bit_a.schematic
Synthesizing work.dff_2.schematic
Synthesizing work.super_logic.schematic
Synthesizing work.super_cell.behavioral
Post processing for work.super_cell.behavioral
@W: CL162 :"C:\pasic\spde\data\macros.vhd":9020:18:9020:19|qz is not assigned a value (floating) 
@W: CL162 :"C:\pasic\spde\data\macros.vhd":9019:17:9019:19|q2z is not assigned a value (floating) 
@W: CL159 :"C:\pasic\spde\data\macros.vhd":9010:18:9010:19|Input pp is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":9011:18:9011:19|Input ps is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":9012:18:9012:19|Input qc is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":9013:18:9013:19|Input qr is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":9014:18:9014:19|Input qs is unused
Post processing for work.super_logic.schematic
Post processing for work.dff_2.schematic
Synthesizing work.rg16_25um.schematic
Post processing for work.rg16_25um.schematic
Synthesizing work.ckpad_25um.schematic
Synthesizing work.ckcell_25um.behavioral
Post processing for work.ckcell_25um.behavioral
Post processing for work.ckpad_25um.schematic
Synthesizing work.inpad_25um.schematic
Synthesizing work.eio_cell.behavioral
Post processing for work.eio_cell.behavioral
@W: CL162 :"C:\pasic\spde\data\macros.vhd":8141:10:8141:18|oqq_dummy is not assigned a value (floating) 
@W: CL162 :"C:\pasic\spde\data\macros.vhd":8140:28:8140:30|eqz is not assigned a value (floating) 
@W: CL162 :"C:\pasic\spde\data\macros.vhd":8128:17:8128:19|iqq is not assigned a value (floating) 
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8119:17:8119:19|Input eqe is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8120:16:8120:19|Input esel is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8122:17:8122:19|Input iqc is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8123:17:8123:19|Input iqe is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8124:17:8124:19|Input iqr is unused
@W: CL159 :"C:\pasic\spde\data\macros.vhd":8126:16:8126:19|Input osel is unused
Post processing for work.inpad_25um.schematic
Synthesizing work.opad16_25um.schematic
Synthesizing work.outpad_25um.schematic
Post processing for work.outpad_25um.schematic
Post processing for work.opad16_25um.schematic
Synthesizing work.counter_en_16bit_a.schematic
Synthesizing work.counter_en_8bit_a_i.schematic
Synthesizing work.counter_en_h4bit.schematic
Post processing for work.counter_en_h4bit.schematic
Post processing for work.counter_en_8bit_a_i.schematic
Synthesizing work.counter_en_8bit_a_ii.schematic
Synthesizing work.counter_en_4bit.schematic
Post processing for work.counter_en_4bit.schematic
Post processing for work.counter_en_8bit_a_ii.schematic
Post processing for work.counter_en_16bit_a.schematic
Post processing for work.example_en_16bit_a.schematic
@END
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################[
Synplicity QuickLogic Technology Mapper, version 7.3.5, Build 222R, built Feb  5 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 16
Loading Properties file: C:\CUST_Supp\Optimised_Counters\eclipseII_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.sc
Automatic dissolve at startup in view:work.COUNTER_EN_8BIT_A_II(schematic) of I1(COUNTER_EN_4BIT)
Automatic dissolve at startup in view:work.COUNTER_EN_8BIT_A_II(schematic) of I4(COUNTER_EN_H4BIT)
Automatic dissolve at startup in view:work.COUNTER_EN_8BIT_A_I(schematic) of I7(COUNTER_EN_H4BIT)
Automatic dissolve at startup in view:work.COUNTER_EN_8BIT_A_I(schematic) of I8(COUNTER_EN_H4BIT)
Automatic dissolve at startup in view:work.COUNTER_EN_16BIT_A(schematic) of I7(COUNTER_EN_8BIT_A_I)
Automatic dissolve at startup in view:work.COUNTER_EN_16BIT_A(schematic) of I6(COUNTER_EN_8BIT_A_II)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I5(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I4(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I3(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I2(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I9(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I8(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I7(DFF_2)
Automatic dissolve at startup in view:work.RG16_25UM(schematic) of I6(DFF_2)
Automatic dissolve at startup in view:work.example_en_16bit_a(schematic) of I6(DFF_2)
Automatic dissolve at startup in view:work.example_en_16bit_a(schematic) of I5(RG16_25UM)
Automatic dissolve at startup in view:work.example_en_16bit_a(schematic) of I1(OPAD16_25UM)
Automatic dissolve at startup in view:work.example_en_16bit_a(schematic) of I9(COUNTER_EN_16BIT_A)
Fanout correction:
No nets needed buffering/replication
---------------------------------------
Resource Usage Report
Part: ql8325

Area estimate:  19 Cells
Register count: 0
Latch count:    0
I/O cells:      19

Details:
CKPAD_25UM:       2
INPAD_25UM:       1
OUTPAD_25UM:     16

SUPER_LOGIC:     19 (area 1)

Found clock example_en_16bit_a|clear_in with period 1000.00ns 
Found clock example_en_16bit_a|clk_in with period 1000.00ns 
@W: MT186 :"c:\cust_supp\optimised_counters\eclipseii_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.vhd":188:3:188:4|Blackbox <SUPER_LOGIC> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT186 :"c:\pasic\spde\data\macros.vhd":10796:3:10796:4|Blackbox <OUTPAD_25UM> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT186 :"c:\cust_supp\optimised_counters\eclipseii_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.vhd":509:3:509:4|Blackbox <INPAD_25UM> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 
@W: MT186 :"c:\cust_supp\optimised_counters\eclipseii_counters\example_counter\area_counter\area_counter_16bit\example_en_16bit_a.vhd":511:3:511:4|Blackbox <CKPAD_25UM> is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Aug 18 17:03:14 2004
#


Top view:               example_en_16bit_a
Requested Frequency:    1.0 MHz
Wire load mode:         top
Wire load model:        pASICQDSP
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..



Performance Summary 
*******************


Worst slack in design: 1000.000

                   Requested     Estimated     Requested     Estimated                  Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack        Type       Group           
-------------------------------------------------------------------------------------------------------------------
System             1.0 MHz       NA            1000.000      0.000         1000.000     system     default_clkgroup
===================================================================================================================