example_en_16bit_a.chp

VHDL examples for counter design, use QuickLogic eclips

    term GND end
    term VCC end
  end
  gate PLL_OUTPAD_25UM cell PLLOUTPAD
    term S port SEL end
    term P port IP end
    term A port IZ end
    term GND end
    term VCC end
  end
  gate PLL_RSTPAD_25UM cell PLLRSTPAD
    term Q port IZ end
    term P port IP end
    term GND end
    term VCC end
  end
  gate PLL_CLKPAD_25UM cell CLOCK
    term O port OP end
    term Q port IC end
    term P port IP end
    term GND end
    term VCC end
  end
  gate CLK2HWCLK cell HWCLOCK
    term P port IP end
    term Q port IC end
  end
end
logical example_en_16bit_a
  gates 38
  nets 71
  gate I9.I6.I4.I1 master SUPER_LOGIC end
  gate I9.I6.I4.I2 master SUPER_LOGIC end
  gate I9.I6.I1.I1 master SUPER_LOGIC end
  gate I9.I6.I1.I2 master SUPER_LOGIC end
  gate I9.I7.I8.I1 master SUPER_LOGIC end
  gate I9.I7.I8.I2 master SUPER_LOGIC end
  gate I9.I7.I7.I1 master SUPER_LOGIC end
  gate I9.I7.I7.I2 master SUPER_LOGIC end
  gate I9.I7.I1 master SUPER_LOGIC end
  gate I9.I7.I2 master SUPER_LOGIC end
  gate I1.I1 master OUTPAD_25UM end
  gate I1.I2 master OUTPAD_25UM end
  gate I1.I3 master OUTPAD_25UM end
  gate I1.I4 master OUTPAD_25UM end
  gate I1.I5 master OUTPAD_25UM end
  gate I1.I6 master OUTPAD_25UM end
  gate I1.I7 master OUTPAD_25UM end
  gate I1.I8 master OUTPAD_25UM end
  gate I1.I9 master OUTPAD_25UM end
  gate I1.I10 master OUTPAD_25UM end
  gate I1.I11 master OUTPAD_25UM end
  gate I1.I12 master OUTPAD_25UM end
  gate I1.I13 master OUTPAD_25UM end
  gate I1.I14 master OUTPAD_25UM end
  gate I1.I15 master OUTPAD_25UM end
  gate I1.I16 master OUTPAD_25UM end
  gate I2 master INPAD_25UM end
  gate I3 master CKPAD_25UM end
  gate I4 master CLK2HWCLK end
  gate I5.I6.I2 master SUPER_LOGIC end
  gate I5.I7.I2 master SUPER_LOGIC end
  gate I5.I8.I2 master SUPER_LOGIC end
  gate I5.I9.I2 master SUPER_LOGIC end
  gate I5.I2.I2 master SUPER_LOGIC end
  gate I5.I3.I2 master SUPER_LOGIC end
  gate I5.I4.I2 master SUPER_LOGIC end
  gate I5.I5.I2 master SUPER_LOGIC end
  gate I6.I2 master SUPER_LOGIC end
  net clear_in direction INPUT
    gate I3 term P end
  end
  net clk_in direction INPUT
    gate I4 term P end
  end
  net enable_in direction INPUT
    gate I2 term P end
  end
  net count_out[0] direction OUTPUT
    gate I1.I1 term P end
  end
  net count_out[1] direction OUTPUT
    gate I1.I2 term P end
  end
  net count_out[2] direction OUTPUT
    gate I1.I3 term P end
  end
  net count_out[3] direction OUTPUT
    gate I1.I4 term P end
  end
  net count_out[4] direction OUTPUT
    gate I1.I5 term P end
  end
  net count_out[5] direction OUTPUT
    gate I1.I6 term P end
  end
  net count_out[6] direction OUTPUT
    gate I1.I7 term P end
  end
  net count_out[7] direction OUTPUT
    gate I1.I8 term P end
  end
  net count_out[8] direction OUTPUT
    gate I1.I9 term P end
  end
  net count_out[9] direction OUTPUT
    gate I1.I10 term P end
  end
  net count_out[10] direction OUTPUT
    gate I1.I11 term P end
  end
  net count_out[11] direction OUTPUT
    gate I1.I12 term P end
  end
  net count_out[12] direction OUTPUT
    gate I1.I13 term P end
  end
  net count_out[13] direction OUTPUT
    gate I1.I14 term P end
  end
  net count_out[14] direction OUTPUT
    gate I1.I15 term P end
  end
  net count_out[15] direction OUTPUT
    gate I1.I16 term P end
  end
  net clear clock 3
    gate I9.I7.I8.I2 term QR end
    gate I9.I7.I8.I1 term QR end
    gate I9.I7.I7.I2 term QR end
    gate I9.I7.I7.I1 term QR end
    gate I9.I6.I4.I2 term QR end
    gate I9.I6.I4.I1 term QR end
    gate I9.I6.I1.I2 term QR end
    gate I9.I6.I1.I1 term QR end
    gate I3 term Q end
  end
  net clk clock 1
    gate I5.I2.I2 term DCLK end
    gate I5.I3.I2 term DCLK end
    gate I5.I4.I2 term DCLK end
    gate I5.I5.I2 term DCLK end
    gate I5.I6.I2 term DCLK end
    gate I5.I7.I2 term DCLK end
    gate I5.I8.I2 term DCLK end
    gate I5.I9.I2 term DCLK end
    gate I6.I2 term DCLK end
    gate I9.I6.I1.I1 term DCLK end
    gate I9.I6.I1.I2 term DCLK end
    gate I9.I6.I4.I1 term DCLK end
    gate I9.I6.I4.I2 term DCLK end
    gate I9.I7.I7.I1 term DCLK end
    gate I9.I7.I7.I2 term DCLK end
    gate I9.I7.I8.I1 term DCLK end
    gate I9.I7.I8.I2 term DCLK end
    gate I4 term Q end
  end
  net enable_reg
    gate I9.I7.I8.I2 term D1 end
    gate I9.I7.I8.I2 term E2 end
    gate I9.I7.I8.I2 term MP end
    gate I9.I7.I8.I1 term F1 end
    gate I9.I7.I1 term F5 end
    gate I6.I2 term QZ end
  end
  net count[0]
    gate I9.I7.I8.I2 term D2 end
    gate I9.I7.I8.I2 term E1 end
    gate I9.I7.I8.I2 term F5 end
    gate I9.I7.I8.I2 term NS end
    gate I9.I7.I8.I1 term F3 end
    gate I9.I7.I1 term A1 end
    gate I5.I5.I2 term E1 end
    gate I9.I7.I8.I2 term Q2Z end
  end
  net count[1]
    gate I9.I7.I8.I2 term F3 end
    gate I9.I7.I8.I1 term B2 end
    gate I9.I7.I8.I1 term C1 end
    gate I9.I7.I8.I1 term MS end
    gate I9.I7.I8.I1 term NP end
    gate I9.I7.I1 term A3 end
    gate I5.I5.I2 term PS end
    gate I9.I7.I8.I1 term QZ end
  end
  net count[2]
    gate I9.I7.I8.I2 term F1 end
    gate I9.I7.I8.I1 term D1 end
    gate I9.I7.I8.I1 term E2 end
    gate I9.I7.I1 term A5 end
    gate I5.I4.I2 term E1 end
    gate I9.I7.I8.I1 term Q2Z end
  end
  net count[3]
    gate I9.I7.I8.I2 term B1 end
    gate I9.I7.I8.I2 term C2 end
    gate I9.I7.I8.I1 term A5 end
    gate I9.I7.I2 term A1 end
    gate I5.I4.I2 term PS end
    gate I9.I7.I8.I2 term QZ end
  end
  net count[4]
    gate I9.I7.I7.I2 term D2 end
    gate I9.I7.I7.I2 term E1 end
    gate I9.I7.I7.I2 term F5 end
    gate I9.I7.I7.I2 term NS end
    gate I9.I7.I7.I1 term F3 end
    gate I9.I7.I2 term A3 end
    gate I5.I3.I2 term E1 end
    gate I9.I7.I7.I2 term Q2Z end
  end
  net count[5]
    gate I9.I7.I7.I2 term F3 end
    gate I9.I7.I7.I1 term B2 end
    gate I9.I7.I7.I1 term C1 end
    gate I9.I7.I7.I1 term MS end
    gate I9.I7.I7.I1 term NP end
    gate I9.I7.I2 term A5 end
    gate I5.I3.I2 term PS end
    gate I9.I7.I7.I1 term QZ end
  end
  net count[6]
    gate I9.I7.I7.I2 term F1 end
    gate I9.I7.I7.I1 term D1 end
    gate I9.I7.I7.I1 term E2 end
    gate I9.I7.I1 term F1 end
    gate I5.I2.I2 term E1 end
    gate I9.I7.I7.I1 term Q2Z end
  end
  net count[7]
    gate I9.I7.I7.I2 term B1 end
    gate I9.I7.I7.I2 term C2 end
    gate I9.I7.I7.I1 term A5 end
    gate I9.I7.I1 term F3 end
    gate I5.I2.I2 term PS end
    gate I9.I7.I7.I2 term QZ end
  end
  net count[8]
    gate I9.I6.I4.I2 term D2 end
    gate I9.I6.I4.I2 term E1 end
    gate I9.I6.I4.I2 term F5 end
    gate I9.I6.I4.I2 term NS end
    gate I9.I6.I4.I1 term F3 end
    gate I5.I9.I2 term E1 end
    gate I9.I6.I4.I2 term Q2Z end
  end
  net count[9]
    gate I9.I6.I4.I2 term F3 end
    gate I9.I6.I4.I1 term B2 end
    gate I9.I6.I4.I1 term C1 end
    gate I9.I6.I4.I1 term MS end
    gate I9.I6.I4.I1 term NP end
    gate I5.I9.I2 term PS end
    gate I9.I6.I4.I1 term QZ end
  end
  net count[10]
    gate I9.I6.I4.I2 term F1 end
    gate I9.I6.I4.I1 term D1 end
    gate I9.I6.I4.I1 term E2 end
    gate I5.I8.I2 term E1 end
    gate I9.I6.I4.I1 term Q2Z end
  end
  net count[11]
    gate I9.I6.I4.I2 term B1 end
    gate I9.I6.I4.I2 term C2 end
    gate I9.I6.I4.I1 term A5 end
    gate I5.I8.I2 term PS end
    gate I9.I6.I4.I2 term QZ end
  end
  net count[12]
    gate I9.I6.I1.I2 term D2 end
    gate I9.I6.I1.I2 term E1 end
    gate I9.I6.I1.I2 term F5 end
    gate I9.I6.I1.I2 term NS end
    gate I9.I6.I1.I1 term F3 end
    gate I5.I7.I2 term E1 end
    gate I9.I6.I1.I2 term Q2Z end
  end
  net count[13]
    gate I9.I6.I1.I2 term F3 end
    gate I9.I6.I1.I1 term B2 end
    gate I9.I6.I1.I1 term C1 end
    gate I9.I6.I1.I1 term MS end
    gate I9.I6.I1.I1 term NP end
    gate I5.I7.I2 term PS end
    gate I9.I6.I1.I1 term QZ end
  end
  net count[14]
    gate I9.I6.I1.I2 term F1 end
    gate I9.I6.I1.I1 term D1 end
    gate I9.I6.I1.I1 term E2 end
    gate I5.I6.I2 term E1 end
    gate I9.I6.I1.I1 term Q2Z end
  end
  net count[15]
    gate I9.I6.I1.I2 term B1 end
    gate I9.I6.I1.I2 term C2 end
    gate I9.I6.I1.I1 term A5 end
    gate I5.I6.I2 term PS end
    gate I9.I6.I1.I2 term QZ end
  end
  net count_reg[0]
    gate I1.I1 term A end
    gate I5.I5.I2 term QZ end
  end
  net count_reg[1]
    gate I1.I2 term A end
    gate I5.I5.I2 term Q2Z end
  end
  net count_reg[2]
    gate I1.I3 term A end
    gate I5.I4.I2 term QZ end
  end
  net count_reg[3]
    gate I1.I4 term A end
    gate I5.I4.I2 term Q2Z end
  end
  net count_reg[4]
    gate I1.I5 term A end
    gate I5.I3.I2 term QZ end
  end
  net count_reg[5]
    gate I1.I6 term A end
    gate I5.I3.I2 term Q2Z end
  end
  net count_reg[6]
    gate I1.I7 term A end
    gate I5.I2.I2 term QZ end
  end
  net count_reg[7]
    gate I1.I8 term A end
    gate I5.I2.I2 term Q2Z end
  end
  net count_reg[8]
    gate I1.I9 term A end
    gate I5.I9.I2 term QZ end
  end
  net count_reg[9]
    gate I1.I10 term A end
    gate I5.I9.I2 term Q2Z end
  end
  net count_reg[10]
    gate I1.I11 term A end
    gate I5.I8.I2 term QZ end
  end
  net count_reg[11]
    gate I1.I12 term A end
    gate I5.I8.I2 term Q2Z end
  end
  net count_reg[12]
    gate I1.I13 term A end
    gate I5.I7.I2 term QZ end
  end
  net count_reg[13]
    gate I1.I14 term A end
    gate I5.I7.I2 term Q2Z end
  end
  net count_reg[14]
    gate I1.I15 term A end
    gate I5.I6.I2 term QZ end
  end
  net count_reg[15]
    gate I1.I16 term A end
    gate I5.I6.I2 term Q2Z end
  end
  net enable
    gate I6.I2 term E1 end
    gate I6.I2 term PS end
    gate I2 term Q end
  end
  net I9.enable_8bit_h
    gate I9.I6.I4.I2 term D1 end
    gate I9.I6.I4.I2 term E2 end
    gate I9.I6.I4.I2 term MP end
    gate I9.I6.I4.I1 term F1 end
    gate I9.I7.I2 term FZ end
  end
  net I9.I7.enableh4bit
    gate I9.I7.I7.I2 term D1 end
    gate I9.I7.I7.I2 term E2 end
    gate I9.I7.I7.I2 term MP end
    gate I9.I7.I7.I1 term F1 end
    gate I9.I7.I8.I1 term AZ end
  end
  net I9.I7.en_8bit1_a
    gate I9.I7.I2 term F1 end
    gate I9.I7.I1 term AZ end
  end
  net I9.I7.en_8bit2_a
    gate I9.I7.I2 term F3 end
    gate I9.I7.I1 term FZ end
  end
  net I9.I7.en_8bit3_a
    gate I9.I7.I2 term F5 end
    gate I9.I7.I2 term AZ end
  end
  net I9.I7.I7.bcd_a
    gate I9.I7.I7.I1 term A1 end
    gate I9.I7.I7.I2 term FZ end
  end
  net I9.I7.I7.ed_a
    gate I9.I7.I7.I1 term A3 end
    gate I9.I7.I7.I1 term B1 end
    gate I9.I7.I7.I1 term C2 end
    gate I9.I7.I7.I1 term FZ end
  end
  net I9.I7.I8.bcd_a
    gate I9.I7.I8.I1 term A1 end
    gate I9.I7.I8.I2 term FZ end
  end
  net I9.I7.I8.ed_a
    gate I9.I7.I8.I1 term A3 end
    gate I9.I7.I8.I1 term B1 end
    gate I9.I7.I8.I1 term C2 end
    gate I9.I7.I8.I1 term FZ end
  end
  net I9.I6.enable_8bit
    gate I9.I6.I1.I2 term D1 end
    gate I9.I6.I1.I2 term E2 end
    gate I9.I6.I1.I2 term MP end
    gate I9.I6.I1.I1 term F1 end
    gate I9.I6.I4.I1 term AZ end
  end
  net I9.I6.I1.bcd_a
    gate I9.I6.I1.I1 term A1 end
    gate I9.I6.I1.I2 term FZ end
  end
  net I9.I6.I1.ed_a
    gate I9.I6.I1.I1 term A3 end
    gate I9.I6.I1.I1 term B1 end
    gate I9.I6.I1.I1 term C2 end
    gate I9.I6.I1.I1 term FZ end
  end
  net I9.I6.I4.bcd_a
    gate I9.I6.I4.I1 term A1 end
    gate I9.I6.I4.I2 term FZ end
  end
  net I9.I6.I4.ed_a
    gate I9.I6.I4.I1 term A3 end
    gate I9.I6.I4.I1 term B1 end
    gate I9.I6.I4.I1 term C2 end
    gate I9.I6.I4.I1 term FZ end
  end
  net GND
    gate I9.I6.I4.I1 term CLKSEL end
    gate I9.I6.I4.I1 term A2 end
    gate I9.I6.I4.I1 term A4 end
    gate I9.I6.I4.I1 term A6 end
    gate I9.I6.I4.I1 term D2 end
    gate I9.I6.I4.I1 term F2 end
    gate I9.I6.I4.I1 term F4 end
    gate I9.I6.I4.I1 term F6 end
    gate I9.I6.I4.I1 term MP end
    gate I9.I6.I4.I1 term NS end
    gate I9.I6.I4.I1 term OP end
    gate I9.I6.I4.I1 term OS end
    gate I9.I6.I4.I1 term PP end
    gate I9.I6.I4.I1 term PS end
    gate I9.I6.I4.I1 term QC end
    gate I9.I6.I4.I1 term QS end
    gate I9.I6.I4.I2 term CLKSEL end
    gate I9.I6.I4.I2 term A2 end
    gate I9.I6.I4.I2 term A4 end
    gate I9.I6.I4.I2 term A6 end
    gate I9.I6.I4.I2 term B2 end
    gate I9.I6.I4.I2 term F2 end
    gate I9.I6.I4.I2 term F4 end
    gate I9.I6.I4.I2 term F6 end
    gate I9.I6.I4.I2 term MS end
    gate I9.I6.I4.I2 term NP end
    gate I9.I6.I4.I2 term OP end
    gate I9.I6.I4.I2 term OS end
    gate I9.I6.I4.I2 term PP end
    gate I9.I6.I4.I2 term PS end
    gate I9.I6.I4.I2 term QC end
    gate I9.I6.I4.I2 term QS end
    gate I9.I6.I1.I1 term CLKSEL end
    gate I9.I6.I1.I1 term A2 end
    gate I9.I6.I1.I1 term A4 end
    gate I9.I6.I1.I1 term A6 end
    gate I9.I6.I1.I1 term D2 end
    gate I9.I6.I1.I1 term F2 end
    gate I9.I6.I1.I1 term F4 end
    gate I9.I6.I1.I1 term F6 end
    gate I9.I6.I1.I1 term MP end
    gate I9.I6.I1.I1 term NS end