example_en_16bit_a.qdf

VHDL examples for counter design, use QuickLogic eclips

#
# Synplify QuickLogic Technology Mapper, version 7.3.5, Build 222R
# Copyright (C) 1994-1995, Synplicity Inc.  All Rights Reserved
#
# File written on: Wed Aug 18 17:03:14 2004
QDIF 3
file ql8325
package pq208
tools
  design 3000
  logic optimizer 0
    option IgnorePack boolean false
  delay modeler 0
    option SpeedGrade string 6
end
library QDIF
 gates 4
 terms 47
 ports 110
 gate CKPAD_25UM cell CLOCK
   term P port IP end
   term Q port IC end
 end
 gate INPAD_25UM cell BIDIR
   term P port IP end
   term Q port IZ end
   term VCC port EQE port ESEL port OQI port OSEL end
   term GND port IE port IQC port IQE port IQR end
 end
 gate OUTPAD_25UM cell BIDIR
   term A port OQI end
   term P port IP end
   term VCC port EQE port ESEL port IE port OSEL end
   term GND port IQC port IQE port IQR end
 end
 gate SUPER_LOGIC cell LOGIC
   term A1 port A1 end
   term A2 port A2 end
   term A3 port A3 end
   term A4 port A4 end
   term A5 port A5 end
   term A6 port A6 end
   term B1 port B1 end
   term B2 port B2 end
   term C1 port C1 end
   term C2 port C2 end
   term D1 port D1 end
   term D2 port D2 end
   term E1 port E1 end
   term E2 port E2 end
   term F1 port F1 end
   term F2 port F2 end
   term F3 port F3 end
   term F4 port F4 end
   term F5 port F5 end
   term F6 port F6 end
   term MP port MP end
   term MS port MS end
   term NP port NP end
   term NS port NS end
   term OP port OP end
   term OS port OS end
   term PP port PP end
   term PS port PS end
   term QC port QC end
   term QR port QR end
   term QS port QS end
   term AZ port AZ end
   term FZ port FZ end
   term NZ port NZ end
   term OZ port OZ end
   term Q2Z port Q2Z end
   term QZ port QZ end
 end
end
logical QDIF
  gates 38
  nets 138
  # instances
  gate I9.I6.I4.I1 master SUPER_LOGIC end
  gate I9.I6.I4.I2 master SUPER_LOGIC end
  gate I9.I6.I1.I1 master SUPER_LOGIC end
  gate I9.I6.I1.I2 master SUPER_LOGIC end
  gate I9.I7.I8.I1 master SUPER_LOGIC end
  gate I9.I7.I8.I2 master SUPER_LOGIC end
  gate I9.I7.I7.I1 master SUPER_LOGIC end
  gate I9.I7.I7.I2 master SUPER_LOGIC end
  gate I9.I7.I1 master SUPER_LOGIC end
  gate I9.I7.I2 master SUPER_LOGIC end
  gate I1.I1 master OUTPAD_25UM end
  gate I1.I2 master OUTPAD_25UM end
  gate I1.I3 master OUTPAD_25UM end
  gate I1.I4 master OUTPAD_25UM end
  gate I1.I5 master OUTPAD_25UM end
  gate I1.I6 master OUTPAD_25UM end
  gate I1.I7 master OUTPAD_25UM end
  gate I1.I8 master OUTPAD_25UM end
  gate I1.I9 master OUTPAD_25UM end
  gate I1.I10 master OUTPAD_25UM end
  gate I1.I11 master OUTPAD_25UM end
  gate I1.I12 master OUTPAD_25UM end
  gate I1.I13 master OUTPAD_25UM end
  gate I1.I14 master OUTPAD_25UM end
  gate I1.I15 master OUTPAD_25UM end
  gate I1.I16 master OUTPAD_25UM end
  gate I2 master INPAD_25UM end
  gate I3 master CKPAD_25UM end
  gate I4 master CKPAD_25UM end
  gate I5.I6.I2 master SUPER_LOGIC end
  gate I5.I7.I2 master SUPER_LOGIC end
  gate I5.I8.I2 master SUPER_LOGIC end
  gate I5.I9.I2 master SUPER_LOGIC end
  gate I5.I2.I2 master SUPER_LOGIC end
  gate I5.I3.I2 master SUPER_LOGIC end
  gate I5.I4.I2 master SUPER_LOGIC end
  gate I5.I5.I2 master SUPER_LOGIC end
  gate I6.I2 master SUPER_LOGIC end
  # Port nets
  net clear_in direction input
    gate I3 term P end
  end
  net clk_in direction input
    gate I4 term P end
  end
  net enable_in direction input
    gate I2 term P end
  end
  net count_out[0] direction output
    gate I1.I1 term P end
  end
  net count_out[1] direction output
    gate I1.I2 term P end
  end
  net count_out[2] direction output
    gate I1.I3 term P end
  end
  net count_out[3] direction output
    gate I1.I4 term P end
  end
  net count_out[4] direction output
    gate I1.I5 term P end
  end
  net count_out[5] direction output
    gate I1.I6 term P end
  end
  net count_out[6] direction output
    gate I1.I7 term P end
  end
  net count_out[7] direction output
    gate I1.I8 term P end
  end
  net count_out[8] direction output
    gate I1.I9 term P end
  end
  net count_out[9] direction output
    gate I1.I10 term P end
  end
  net count_out[10] direction output
    gate I1.I11 term P end
  end
  net count_out[11] direction output
    gate I1.I12 term P end
  end
  net count_out[12] direction output
    gate I1.I13 term P end
  end
  net count_out[13] direction output
    gate I1.I14 term P end
  end
  net count_out[14] direction output
    gate I1.I15 term P end
  end
  net count_out[15] direction output
    gate I1.I16 term P end
  end
  # Internal nets
  net clear
    gate I3 term Q end
    gate I9.I6.I1.I1 term QR end
    gate I9.I6.I1.I2 term QR end
    gate I9.I6.I4.I1 term QR end
    gate I9.I6.I4.I2 term QR end
    gate I9.I7.I7.I1 term QR end
    gate I9.I7.I7.I2 term QR end
    gate I9.I7.I8.I1 term QR end
    gate I9.I7.I8.I2 term QR end
  end
  net clk
    gate I4 term Q end
    gate I5.I2.I2 term QC end
    gate I5.I3.I2 term QC end
    gate I5.I4.I2 term QC end
    gate I5.I5.I2 term QC end
    gate I5.I6.I2 term QC end
    gate I5.I7.I2 term QC end
    gate I5.I8.I2 term QC end
    gate I5.I9.I2 term QC end
    gate I6.I2 term QC end
    gate I9.I6.I1.I1 term QC end
    gate I9.I6.I1.I2 term QC end
    gate I9.I6.I4.I1 term QC end
    gate I9.I6.I4.I2 term QC end
    gate I9.I7.I7.I1 term QC end
    gate I9.I7.I7.I2 term QC end
    gate I9.I7.I8.I1 term QC end
    gate I9.I7.I8.I2 term QC end
  end
  net enable_reg
    gate I6.I2 term QZ end
    gate I9.I7.I1 term F5 end
    gate I9.I7.I8.I1 term F1 end
    gate I9.I7.I8.I2 term MP end
    gate I9.I7.I8.I2 term E2 end
    gate I9.I7.I8.I2 term D1 end
  end
  net count[0]
    gate I9.I7.I8.I2 term Q2Z end
    gate I5.I5.I2 term E1 end
    gate I9.I7.I1 term A1 end
    gate I9.I7.I8.I1 term F3 end
    gate I9.I7.I8.I2 term NS end
    gate I9.I7.I8.I2 term F5 end
    gate I9.I7.I8.I2 term E1 end
    gate I9.I7.I8.I2 term D2 end
  end
  net count[1]
    gate I9.I7.I8.I1 term QZ end
    gate I5.I5.I2 term PS end
    gate I9.I7.I1 term A3 end
    gate I9.I7.I8.I1 term NP end
    gate I9.I7.I8.I1 term MS end
    gate I9.I7.I8.I1 term C1 end
    gate I9.I7.I8.I1 term B2 end
    gate I9.I7.I8.I2 term F3 end
  end
  net count[2]
    gate I9.I7.I8.I1 term Q2Z end
    gate I5.I4.I2 term E1 end
    gate I9.I7.I1 term A5 end
    gate I9.I7.I8.I1 term E2 end
    gate I9.I7.I8.I1 term D1 end
    gate I9.I7.I8.I2 term F1 end
  end
  net count[3]
    gate I9.I7.I8.I2 term QZ end
    gate I5.I4.I2 term PS end
    gate I9.I7.I2 term A1 end
    gate I9.I7.I8.I1 term A5 end
    gate I9.I7.I8.I2 term C2 end
    gate I9.I7.I8.I2 term B1 end
  end
  net count[4]
    gate I9.I7.I7.I2 term Q2Z end
    gate I5.I3.I2 term E1 end
    gate I9.I7.I2 term A3 end
    gate I9.I7.I7.I1 term F3 end
    gate I9.I7.I7.I2 term NS end
    gate I9.I7.I7.I2 term F5 end
    gate I9.I7.I7.I2 term E1 end
    gate I9.I7.I7.I2 term D2 end
  end
  net count[5]
    gate I9.I7.I7.I1 term QZ end
    gate I5.I3.I2 term PS end
    gate I9.I7.I2 term A5 end
    gate I9.I7.I7.I1 term NP end
    gate I9.I7.I7.I1 term MS end
    gate I9.I7.I7.I1 term C1 end
    gate I9.I7.I7.I1 term B2 end
    gate I9.I7.I7.I2 term F3 end
  end
  net count[6]
    gate I9.I7.I7.I1 term Q2Z end
    gate I5.I2.I2 term E1 end
    gate I9.I7.I1 term F1 end
    gate I9.I7.I7.I1 term E2 end
    gate I9.I7.I7.I1 term D1 end
    gate I9.I7.I7.I2 term F1 end
  end
  net count[7]
    gate I9.I7.I7.I2 term QZ end
    gate I5.I2.I2 term PS end
    gate I9.I7.I1 term F3 end
    gate I9.I7.I7.I1 term A5 end
    gate I9.I7.I7.I2 term C2 end
    gate I9.I7.I7.I2 term B1 end
  end
  net count[8]
    gate I9.I6.I4.I2 term Q2Z end
    gate I5.I9.I2 term E1 end
    gate I9.I6.I4.I1 term F3 end
    gate I9.I6.I4.I2 term NS end
    gate I9.I6.I4.I2 term F5 end
    gate I9.I6.I4.I2 term E1 end
    gate I9.I6.I4.I2 term D2 end
  end
  net count[9]
    gate I9.I6.I4.I1 term QZ end
    gate I5.I9.I2 term PS end
    gate I9.I6.I4.I1 term NP end
    gate I9.I6.I4.I1 term MS end
    gate I9.I6.I4.I1 term C1 end
    gate I9.I6.I4.I1 term B2 end
    gate I9.I6.I4.I2 term F3 end
  end
  net count[10]
    gate I9.I6.I4.I1 term Q2Z end
    gate I5.I8.I2 term E1 end
    gate I9.I6.I4.I1 term E2 end
    gate I9.I6.I4.I1 term D1 end
    gate I9.I6.I4.I2 term F1 end
  end
  net count[11]
    gate I9.I6.I4.I2 term QZ end
    gate I5.I8.I2 term PS end
    gate I9.I6.I4.I1 term A5 end
    gate I9.I6.I4.I2 term C2 end
    gate I9.I6.I4.I2 term B1 end
  end
  net count[12]
    gate I9.I6.I1.I2 term Q2Z end
    gate I5.I7.I2 term E1 end
    gate I9.I6.I1.I1 term F3 end
    gate I9.I6.I1.I2 term NS end
    gate I9.I6.I1.I2 term F5 end
    gate I9.I6.I1.I2 term E1 end
    gate I9.I6.I1.I2 term D2 end
  end
  net count[13]
    gate I9.I6.I1.I1 term QZ end
    gate I5.I7.I2 term PS end
    gate I9.I6.I1.I1 term NP end
    gate I9.I6.I1.I1 term MS end
    gate I9.I6.I1.I1 term C1 end
    gate I9.I6.I1.I1 term B2 end
    gate I9.I6.I1.I2 term F3 end
  end
  net count[14]
    gate I9.I6.I1.I1 term Q2Z end
    gate I5.I6.I2 term E1 end
    gate I9.I6.I1.I1 term E2 end
    gate I9.I6.I1.I1 term D1 end
    gate I9.I6.I1.I2 term F1 end
  end
  net count[15]
    gate I9.I6.I1.I2 term QZ end
    gate I5.I6.I2 term PS end
    gate I9.I6.I1.I1 term A5 end
    gate I9.I6.I1.I2 term C2 end
    gate I9.I6.I1.I2 term B1 end
  end
  net count_reg[0]
    gate I5.I5.I2 term QZ end
    gate I1.I1 term A end
  end
  net count_reg[1]
    gate I5.I5.I2 term Q2Z end
    gate I1.I2 term A end
  end
  net count_reg[2]
    gate I5.I4.I2 term QZ end
    gate I1.I3 term A end
  end
  net count_reg[3]
    gate I5.I4.I2 term Q2Z end
    gate I1.I4 term A end
  end
  net count_reg[4]
    gate I5.I3.I2 term QZ end
    gate I1.I5 term A end
  end
  net count_reg[5]
    gate I5.I3.I2 term Q2Z end
    gate I1.I6 term A end
  end
  net count_reg[6]
    gate I5.I2.I2 term QZ end
    gate I1.I7 term A end
  end
  net count_reg[7]
    gate I5.I2.I2 term Q2Z end
    gate I1.I8 term A end
  end
  net count_reg[8]
    gate I5.I9.I2 term QZ end
    gate I1.I9 term A end
  end
  net count_reg[9]
    gate I5.I9.I2 term Q2Z end
    gate I1.I10 term A end
  end
  net count_reg[10]
    gate I5.I8.I2 term QZ end
    gate I1.I11 term A end
  end
  net count_reg[11]
    gate I5.I8.I2 term Q2Z end
    gate I1.I12 term A end
  end
  net count_reg[12]
    gate I5.I7.I2 term QZ end
    gate I1.I13 term A end
  end
  net count_reg[13]
    gate I5.I7.I2 term Q2Z end
    gate I1.I14 term A end
  end
  net count_reg[14]
    gate I5.I6.I2 term QZ end
    gate I1.I15 term A end
  end
  net count_reg[15]
    gate I5.I6.I2 term Q2Z end
    gate I1.I16 term A end
  end
  net enable
    gate I2 term Q end
    gate I6.I2 term PS end
    gate I6.I2 term E1 end
  end
  net VCC
    gate I5.I2.I2 term B1 end
    gate I5.I2.I2 term A5 end
    gate I5.I2.I2 term A3 end
    gate I5.I2.I2 term A1 end
    gate I5.I2.I2 term MS end
    gate I5.I2.I2 term PP end
    gate I5.I2.I2 term OS end
    gate I5.I2.I2 term NS end
    gate I5.I2.I2 term D1 end
    gate I5.I2.I2 term F5 end
    gate I5.I2.I2 term F3 end
    gate I5.I2.I2 term F1 end
    gate I5.I2.I2 term C1 end
    gate I5.I3.I2 term A1 end
    gate I5.I3.I2 term B1 end
    gate I5.I3.I2 term A5 end
    gate I5.I3.I2 term A3 end
    gate I5.I3.I2 term MS end
    gate I5.I3.I2 term PP end
    gate I5.I3.I2 term OS end
    gate I5.I3.I2 term NS end
    gate I5.I3.I2 term D1 end
    gate I5.I3.I2 term F5 end
    gate I5.I3.I2 term F3 end
    gate I5.I3.I2 term F1 end
    gate I5.I3.I2 term C1 end
    gate I5.I4.I2 term A1 end
    gate I5.I4.I2 term B1 end
    gate I5.I4.I2 term A5 end
    gate I5.I4.I2 term A3 end
    gate I5.I4.I2 term MS end
    gate I5.I4.I2 term PP end
    gate I5.I4.I2 term OS end
    gate I5.I4.I2 term NS end
    gate I5.I4.I2 term D1 end
    gate I5.I4.I2 term F5 end
    gate I5.I4.I2 term F3 end
    gate I5.I4.I2 term F1 end
    gate I5.I4.I2 term C1 end
    gate I5.I5.I2 term A1 end
    gate I5.I5.I2 term C1 end
    gate I5.I5.I2 term B1 end
    gate I5.I5.I2 term A5 end
    gate I5.I5.I2 term A3 end
    gate I5.I5.I2 term NS end
    gate I5.I5.I2 term MS end
    gate I5.I5.I2 term PP end
    gate I5.I5.I2 term OS end